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Generally all looks good. Just a few minor nit-picks
rahahahat
previously approved these changes
Aug 16, 2023
FinnWilkinson
previously approved these changes
Oct 10, 2023
dANW34V3R
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Oct 11, 2023
FinnWilkinson
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Oct 11, 2023
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FinnWilkinson
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Nov 2, 2023
This PR for the most part addresses issue #329 - correcting the SVCR and Streaming Mode logic introduced with SME. This is summaried as: - If a program is in Streaming Mode and calls SMSTART again, ZA and Vector registers are not zeroed out. - SVE Vector registers (and their aliases such as NEON and Scalar registers) are only zeroed out when SVCR.SM bit changes - SME's ZA register is only zeroed out when SVCR.ZA bit changes - SVCR can now be correctly updated using a regulat msr svcr, xt instruction in addition to smstart/smstop/msr svcr, #imm - More tests surrounding the SVCR logic have been added Additional to this, logic for the NEON muti-struct store with post index instructions introduced in PR #335 has been corrected via a small change to the metadata to correctly identify if a #imm or xt is used as said post index.
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Various new aarch64 instruction support from recent ModSim work.