Unit Test Suite Update

CMakeLists.txt

@@ -215,7 +215,7 @@ endif()
   # saves us from having to build all targets before running the tests
   add_custom_target(test-all
     COMMAND ${CMAKE_CTEST_COMMAND}
-    DEPENDS unittests regression-aarch64 regression-riscv
+    DEPENDS unittests regression-aarch64 regression-riscv integrationtests
   )
 endif()
 

configs/DEMO_RISCV.yaml

@@ -139,7 +139,7 @@ Latencies:
 CPU-Info:
   # Set Generate-Special-Dir to 'T' to generate the special files directory, or to 'F' to not.
   # (Not generating the special files directory may require the user to copy over files manually)
-  Generate-Special-Dir: true
+  Generate-Special-Dir: True
   # Core-Count MUST be 1 as multi-core is not supported at this time. (TX2 true value is 32)
   Core-Count: 1
   # Socket-Count MUST be 1 as multi-socket simulations are not supported at this time. (TX2 true value is 2)

docs/sphinx/user/configuring_simeng.rst

@@ -349,9 +349,20 @@ CPU Info
     These fields are currently only used to generate a replica of the required Special Files directory structure.
 
 Generate-Special-Dir
-    Values are either "True" or "False".
-    Dictates whether or not SimEng should generate the SpecialFiles directory tree at runtime.
-    The alternative to this would be to copy in the required SpecialFiles by hand.
+    Values are either `True` or `False`.
+    Dictates whether or not SimEng should generate the Special-Files directory tree at runtime.
+    If your code requires Special-Files but you wish to use your own / existing files from a real system, you will need to set this option to `False`.
+    The files which are currently generated / supported in SimEng are:
+
+        - `/proc/cpuinfo`
+        - `/proc/stat`
+        - `/sys/deviced/system/cpu/online`
+        - `/sys/deviced/system/cpu/cpu{0..CoreCount}/topology/core_id`
+        - `/sys/deviced/system/cpu/cpu{0..CoreCount}/topology/physical_package_id`
+
+Special-File-Dir-Path
+    Represented as a String; is the **absolute path**  to the root directory where the Special-Files will be generated *OR* where existing Special-Files are located.
+    This is optional, and defaults to `SIMENG_BUILD_DIRECTORY/specialFiles`. The root directory must already exist.
 
 Core-Count
     Defines the total number of Physical cores (Not including threads).

src/include/simeng/CoreInstance.hh

@@ -22,7 +22,7 @@
 
 // Program used when no executable is provided; counts down from
 // 1024*1024, with an independent `orr` at the start of each branch.
-uint32_t hex_[] = {
+static uint32_t hex_[] = {
     0x320C03E0,  // orr w0, wzr, #1048576
     0x320003E1,  // orr w0, wzr, #1
     0x71000400,  // subs w0, w0, #1
@@ -102,17 +102,20 @@ class CoreInstance {
   /** Construct the special file directory. */
   void createSpecialFileDirectory();
 
-  /** Whether or not the source has been assembled by LLVM. */
-  bool assembledSource_ = false;
+  /** The config file describing the modelled core to be created. */
+  ryml::ConstNodeRef config_;
+
+  /** The SimEng Linux kernel object. */
+  simeng::kernel::Linux kernel_;
 
   /** Reference to source assembled by LLVM. */
   char* source_ = nullptr;
 
   /** Size of the source code assembled by LLVM. */
   size_t sourceSize_ = 0;
 
-  /** The config file describing the modelled core to be created. */
-  ryml::ConstNodeRef config_;
+  /** Whether or not the source has been assembled by LLVM. */
+  bool assembledSource_ = false;
 
   /** Reference to the SimEng linux process object. */
   std::unique_ptr<simeng::kernel::LinuxProcess> process_ = nullptr;
@@ -123,9 +126,6 @@ class CoreInstance {
   /** The process memory space. */
   std::shared_ptr<char> processMemory_;
 
-  /** The SimEng Linux kernel object. */
-  simeng::kernel::Linux kernel_;
-
   /** Whether or not the dataMemory_ must be set manually. */
   bool setDataMemory_ = false;
 

src/include/simeng/Instruction.hh

@@ -256,7 +256,7 @@ class Instruction {
 
   /** An arbitrary index value for the micro-operation. Its use is based on the
    * implementation of specific micro-operations. */
-  int microOpIndex_;
+  int microOpIndex_ = 0;
 };
 
 }  // namespace simeng

src/include/simeng/RegisterValue.hh

@@ -131,4 +131,16 @@ class RegisterValue {
   alignas(8) char value[MAX_LOCAL_BYTES];
 };
 
+inline bool operator==(const RegisterValue& lhs, const RegisterValue& rhs) {
+  if (lhs.size() == rhs.size()) {
+    auto lhV = lhs.getAsVector<char>();
+    auto rhV = rhs.getAsVector<char>();
+    for (int i = 0; i < lhs.size(); i++) {
+      if (lhV[i] != rhV[i]) return false;
+    }
+    return true;
+  }
+  return false;
+}
+
 }  // namespace simeng

src/include/simeng/SpecialFileDirGen.hh

@@ -4,7 +4,6 @@
 #include <string>
 
 #include "simeng/config/SimInfo.hh"
-#include "simeng/version.hh"
 
 namespace simeng {
 class SpecialFileDirGen {
@@ -22,7 +21,7 @@ class SpecialFileDirGen {
 
  private:
   /** Path to the root of the SimEng special files directory. */
-  const std::string specialFilesDir_ = SIMENG_BUILD_DIR "/specialFiles";
+  const std::string specialFilesDir_;
 
   /** Values declared in YAML config file needed to create the Special Files
    * Directory tree. */

src/include/simeng/arch/aarch64/ExceptionHandler.hh

@@ -96,6 +96,16 @@ class ExceptionHandler : public simeng::arch::ExceptionHandler {
   static constexpr Register R3 = {RegisterType::GENERAL, 3};
   static constexpr Register R4 = {RegisterType::GENERAL, 4};
   static constexpr Register R5 = {RegisterType::GENERAL, 5};
+
+  /** Let the following ExceptionHandlerTest derived classes be a friend of this
+   * class to allow proper testing of `readStringThen()`, `readBufferThen()` and
+   * `printException()` functions. */
+  friend class AArch64ExceptionHandlerTest_readStringThen_Test;
+  friend class AArch64ExceptionHandlerTest_readStringThen_maxLen0_Test;
+  friend class AArch64ExceptionHandlerTest_readStringThen_maxLenReached_Test;
+  friend class AArch64ExceptionHandlerTest_readBufferThen_Test;
+  friend class AArch64ExceptionHandlerTest_readBufferThen_length0_Test;
+  friend class AArch64ExceptionHandlerTest_printException_Test;
 };
 
 }  // namespace aarch64

src/include/simeng/arch/aarch64/Instruction.hh

@@ -13,38 +13,6 @@ namespace simeng {
 namespace arch {
 namespace aarch64 {
 
-/** Apply the shift specified by `shiftType` to the unsigned integer `value`,
- * shifting by `amount`. */
-template <typename T>
-std::enable_if_t<std::is_integral_v<T> && std::is_unsigned_v<T>, T> shiftValue(
-    T value, uint8_t shiftType, uint8_t amount) {
-  switch (shiftType) {
-    case ARM64_SFT_LSL:
-      return value << amount;
-    case ARM64_SFT_LSR:
-      return value >> amount;
-    case ARM64_SFT_ASR:
-      return static_cast<std::make_signed_t<T>>(value) >> amount;
-    case ARM64_SFT_ROR: {
-      // Assuming sizeof(T) is a power of 2.
-      const auto mask = sizeof(T) * 8 - 1;
-      assert((amount <= mask) && "Rotate amount exceeds type width");
-      amount &= mask;
-      return (value >> amount) | (value << ((-amount) & mask));
-    }
-    case ARM64_SFT_MSL: {
-      // pad in with ones instead of zeros
-      const auto mask = (1 << amount) - 1;
-      return (value << amount) | mask;
-    }
-    case ARM64_SFT_INVALID:
-      return value;
-    default:
-      assert(false && "Unknown shift type");
-      return 0;
-  }
-}
-
 /** Get the size of the data to be accessed from/to memory. */
 inline uint8_t getDataSize(cs_arm64_op op) {
   // Check from top of the range downwards
@@ -203,6 +171,9 @@ const uint8_t NZCV = 3;
 const uint8_t SYSTEM = 4;
 /** The [256-byte x (SVL / 8)] SME matrix register za. */
 const uint8_t MATRIX = 5;
+
+/** A special register value representing the zero register. */
+const Register ZERO_REGISTER = {GENERAL, (uint16_t)-1};
 }  // namespace RegisterType
 
 /** A struct holding user-defined execution information for a aarch64
@@ -222,7 +193,6 @@ struct ExecutionInfo {
 enum class InstructionException {
   None = 0,
   EncodingUnallocated,
-  EncodingNotYetImplemented,
   ExecutionNotYetImplemented,
   AliasNotYetImplemented,
   MisalignedPC,
@@ -366,11 +336,6 @@ class Instruction : public simeng::Instruction {
   /** Retrieve the instruction's associated architecture. */
   const Architecture& getArchitecture() const;
 
-  /** A special register value representing the zero register. If passed to
-   * `setSourceRegisters`/`setDestinationRegisters`, the value will be
-   * automatically supplied as zero. */
-  static const Register ZERO_REGISTER;
-
  private:
   /** A reference to the ISA instance this instruction belongs to. */
   const Architecture& architecture_;
@@ -380,11 +345,10 @@ class Instruction : public simeng::Instruction {
 
   /** A vector of source registers. */
   std::vector<Register> sourceRegisters;
-  /** The number of source registers this instruction reads from. */
-  uint16_t sourceRegisterCount = 0;
 
   /** A vector of destination registers. */
   std::vector<Register> destinationRegisters;
+
   /** The number of destination registers this instruction writes to. */
   uint16_t destinationRegisterCount = 0;
 
@@ -404,15 +368,6 @@ class Instruction : public simeng::Instruction {
    * registers. */
   void decode();
 
-  /** Set the source registers of the instruction, and create a corresponding
-   * operands vector. Zero register references will be pre-supplied with a value
-   * of 0. */
-  void setSourceRegisters(const std::vector<Register>& registers);
-
-  /** Set the destination registers for the instruction, and create a
-   * corresponding results vector. */
-  void setDestinationRegisters(const std::vector<Register>& registers);
-
   // Scheduling
   /** The number of operands that have not yet had values supplied. Used to
    * determine execution readiness. */
@@ -499,14 +454,6 @@ class Instruction : public simeng::Instruction {
    * for sending to memory (according to instruction type). Each entry
    * corresponds to a `memoryAddresses` entry. */
   std::vector<RegisterValue> memoryData;
-
-  // Execution helpers
-  /** Extend `value` according to `extendType`, and left-shift the result by
-   * `shift` */
-  uint64_t extendValue(uint64_t value, uint8_t extendType, uint8_t shift) const;
-
-  /** Extend `value` using extension/shifting rules defined in `op`. */
-  uint64_t extendOffset(uint64_t value, const cs_arm64_op& op) const;
 };
 
 }  // namespace aarch64

src/include/simeng/arch/aarch64/MicroDecoder.hh

@@ -30,6 +30,7 @@ class MicroDecoder {
                  const Instruction& macroOp, MacroOp& output,
                  csh capstoneHandle);
 
+ private:
   /** Detect if there's an overlap between the underlying hardware registers
    * (e.g. z5, v5, q5, d5, s5, h5, and b5). */
   bool detectOverlap(arm64_reg registerA, arm64_reg registerB);
@@ -67,7 +68,6 @@ class MicroDecoder {
                            csh capstoneHandle, bool lastMicroOp = false,
                            int microOpIndex = 0, uint8_t dataSize = 0);
 
- private:
   /** Flag to determine whether instruction splitting is enabled. */
   const bool instructionSplit_;