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…dresses correctly so all implementations are left blank
… RISC-V implementation
ABenC377
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Feb 20, 2024
jj16791
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Feb 20, 2024
jj16791
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Needs rebasing onto updated dev |
jj16791
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Feb 20, 2024
JosephMoore25
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JosephMoore25
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Looks all good, nice work
FinnWilkinson
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Approving on the condition that an issue is created which outlines that the following in FetchUnitTest.cc need attending to
- Ensure all tests are parameterised (some for the loop buffer currently are not)
- Check output buffer contains expected macro-op in all tests where relevant
- Rather than hard code the expected next PC value (currently 16 throughout) or value of predecode return (4 often used) use the block size / maxBlockSize respectively in calculations
- Parameterise the block size
dANW34V3R
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FinnWilkinson
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jj16791
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This PR implements the RISC-V compressed instructions and tests. Each instruction is treated like a pseudoinstruction which is expanded during metadata instantiation into a typical rv64g instruction. This means there are no changes to instruction execute.
Immediate values are now extracted during decode and stored in the
immfield.