RISC-V Compressed Instructions

configs/DEMO_RISCV.yaml

@@ -4,6 +4,7 @@
 
 Core:
   ISA: rv64
+  Compressed: True
   Simulation-Mode: outoforder
   Clock-Frequency-GHz: 2.5
   Timer-Frequency-MHz: 200

docs/sphinx/developer/arch/supported/riscv.rst

@@ -1,7 +1,7 @@
 RISCV
 =======
 
-SimEng provides an almost complete implementation of the rv64imafd architecture, as well as being capable of handling some supervisor call (syscall) exceptions via basic system call emulation. This is sufficient to run many simple single threaded programs that have been statically compiled with the standard library.
+SimEng provides an almost complete implementation of the rv64imafdc architecture, as well as being capable of handling some supervisor call (syscall) exceptions via basic system call emulation. This is sufficient to run many simple single threaded programs that have been statically compiled with the standard library.
 
 .. contents:: Contents
 
@@ -57,6 +57,8 @@ Adding execution behaviour
 
 The process for adding a new instruction is very similar to that of :ref:`AArch64 <aarch64-adding-instructions>`, by adding a new, uniquely identified entry to ``src/lib/arch/riscv/Instruction_execute.cc``.
 
+Compressed instructions are treated in the same way as pseudoinstructions. By design they can be expanded to full instructions from the base and floating point extensions. A new case should be added to the switch statement in ``InstructionMetadata`` to perform the relevant adjustment to the metadata. The instruction can then be allowed to flow through the pipeline - no new execute case is necessary.
+
 Zero registers
 **************
 

docs/sphinx/user/configuring_simeng.rst

@@ -52,6 +52,9 @@ Vector-Length (Only in use when ISA is ``AArch64``)
 Streaming-Vector-Length (Only in use when ISA is ``AArch64``)
     The vector length used by instructions belonging to Arm's Scalable Matrix Extension. Although the architecturally valid vector lengths are powers of 2 between 128 and 2048 inclusive, the supported vector lengths are those between 128 and 2048 in increments of 128.
 
+Compressed (Only in use when ISA is ``rv64``)
+    Enables the RISC-V compressed extension. If set to false and compressed instructions are supplied, a misaligned program counter exception is usually thrown.
+
 Fetch
 -----
 

src/include/simeng/arch/Architecture.hh

@@ -74,6 +74,9 @@ class Architecture {
   /** Returns the maximum size of a valid instruction in bytes. */
   virtual uint8_t getMaxInstructionSize() const = 0;
 
+  /** Returns the minimum size of a valid instruction in bytes. */
+  virtual uint8_t getMinInstructionSize() const = 0;
+
   /** Updates System registers of any system-based timers. */
   virtual void updateSystemTimerRegisters(RegisterFileSet* regFile,
                                           const uint64_t iterations) const = 0;

src/include/simeng/arch/aarch64/Architecture.hh

@@ -47,6 +47,9 @@ class Architecture : public arch::Architecture {
   /** Returns the maximum size of a valid instruction in bytes. */
   uint8_t getMaxInstructionSize() const override;
 
+  /** Returns the minimum size of a valid instruction in bytes. */
+  uint8_t getMinInstructionSize() const override;
+
   /** Updates System registers of any system-based timers. */
   void updateSystemTimerRegisters(RegisterFileSet* regFile,
                                   const uint64_t iterations) const override;

src/include/simeng/arch/aarch64/Instruction.hh

@@ -437,8 +437,8 @@ class Instruction : public simeng::Instruction {
   /** The current exception state of this instruction. */
   InstructionException exception_ = InstructionException::None;
 
-  /** The number of operands that have not yet had values supplied. Used to
-   * determine execution readiness. */
+  /** The number of source operands that have not yet had values supplied. Used
+   * to determine execution readiness. */
   uint16_t sourceOperandsPending_ = 0;
 
   /** Is the micro-operation opcode of the instruction, where appropriate. */

src/include/simeng/arch/riscv/ArchInfo.hh

@@ -19,6 +19,14 @@ typedef enum riscv_sysreg {
 
 } riscv_sysreg;
 
+//  A struct of RISC-V specific constants
+namespace constantsPool {
+const uint8_t addressAlignMask = 0x3;
+const uint8_t addressAlignMaskCompressed = 0x1;
+const uint8_t minInstWidthBytes = 4;
+const uint8_t minInstWidthBytesCompressed = 2;
+};  // namespace constantsPool
+
 /** A class to hold and generate riscv specific architecture configuration
  * options. */
 class ArchInfo : public simeng::arch::ArchInfo {

src/include/simeng/arch/riscv/Architecture.hh

@@ -22,8 +22,8 @@ class Architecture : public arch::Architecture {
   ~Architecture();
 
   /** Pre-decode instruction memory into a macro-op of `Instruction`
-   * instances. Returns the number of bytes consumed to produce it (always 4),
-   * and writes into the supplied macro-op vector. */
+   * instances. Returns the number of bytes consumed to produce it (0 if
+   * failure), and writes into the supplied macro-op vector. */
   uint8_t predecode(const void* ptr, uint16_t bytesAvailable,
                     uint64_t instructionAddress,
                     MacroOp& output) const override;
@@ -45,6 +45,9 @@ class Architecture : public arch::Architecture {
   /** Returns the maximum size of a valid instruction in bytes. */
   uint8_t getMaxInstructionSize() const override;
 
+  /** Returns the minimum size of a valid instruction in bytes. */
+  uint8_t getMinInstructionSize() const override;
+
   /** Updates System registers of any system-based timers. */
   void updateSystemTimerRegisters(RegisterFileSet* regFile,
                                   const uint64_t iterations) const override;
@@ -68,6 +71,12 @@ class Architecture : public arch::Architecture {
 
   /** System Register of Processor Cycle Counter. */
   simeng::Register cycleSystemReg_;
+
+  /** A mask used to determine if an address has the correct byte alignment */
+  uint8_t addressAlignmentMask_;
+
+  /** Minimum number of bytes that can represent an instruction */
+  uint8_t minInsnLength_;
 };
 
 }  // namespace riscv

src/include/simeng/arch/riscv/Instruction.hh

@@ -233,15 +233,19 @@ class Instruction : public simeng::Instruction {
    * `sourceRegisters` entry. */
   std::array<RegisterValue, MAX_SOURCE_REGISTERS> sourceValues_;
 
+  /** The immediate source operand for which there is only ever one. Remains 0
+   * if unused. */
+  int64_t sourceImm_ = 0;
+
   /** An array of generated output results. Each entry corresponds to a
    * `destinationRegisters` entry. */
   std::array<RegisterValue, MAX_DESTINATION_REGISTERS> results_;
 
   /** The current exception state of this instruction. */
   InstructionException exception_ = InstructionException::None;
 
-  /** The number of operands that have not yet had values supplied. Used to
-   * determine execution readiness. */
+  /** The number of source operands that have not yet had values supplied. Used
+   * to determine execution readiness. */
   uint16_t sourceOperandsPending_ = 0;
 
   /** Used to denote what type of instruction this is. Utilises the constants in

src/include/simeng/kernel/LinuxProcess.hh

@@ -40,7 +40,7 @@ uint64_t alignToBoundary(uint64_t value, uint64_t boundary);
  *
  * The constructed process follows a typical layout:
  *
- * |---------------| <- start of stack
+ * |---------------| <- start/bottom of stack
  * |     Stack     |    stack grows downwards
  * |-v-----------v-|
  * |               |
@@ -76,7 +76,7 @@ class LinuxProcess {
   /** Get the address of the start of the heap region. */
   uint64_t getHeapStart() const;
 
-  /** Get the address of the top of the stack. */
+  /** Get the address of the bottom of the stack. */
   uint64_t getStackStart() const;
 
   /** Get the address of the start of the mmap region. */
@@ -94,7 +94,7 @@ class LinuxProcess {
   /** Get the entry point. */
   uint64_t getEntryPoint() const;
 
-  /** Get the initial stack pointer address. */
+  /** Get the initial stack pointer. */
   uint64_t getInitialStackPointer() const;
 
   /** Get the path of the executable. */
@@ -134,7 +134,7 @@ class LinuxProcess {
   /** The page size of the process memory. */
   const uint64_t pageSize_ = 4096;
 
-  /** The address of the stack pointer. */
+  /** The address of the head/top of the stack */
   uint64_t stackPointer_;
 
   /** The process image size. */

src/include/simeng/pipeline/FetchUnit.hh

@@ -117,6 +117,13 @@ class FetchUnit {
 
   /** The amount of data currently in the fetch buffer. */
   uint16_t bufferedBytes_ = 0;
+
+  /** Let the following PipelineFetchUnitTest derived classes be a friend of
+   * this class to allow proper testing of 'tick' function. */
+  friend class PipelineFetchUnitTest_invalidMinBytesAtEndOfBuffer_Test;
+  friend class PipelineFetchUnitTest_minSizeInstructionAtEndOfBuffer_Test;
+  friend class PipelineFetchUnitTest_validMinSizeReadsDontComplete_Test;
+  friend class PipelineFetchUnitTest_invalidMinBytesreadsDontComplete_Test;
 };
 
 }  // namespace pipeline

src/lib/arch/aarch64/Architecture.cc

@@ -239,6 +239,8 @@ ProcessStateChange Architecture::getInitialState() const {
 
 uint8_t Architecture::getMaxInstructionSize() const { return 4; }
 
+uint8_t Architecture::getMinInstructionSize() const { return 4; }
+
 void Architecture::updateSystemTimerRegisters(RegisterFileSet* regFile,
                                               const uint64_t iterations) const {
   // Update the Processor Cycle Counter to total cycles completed.

src/lib/arch/riscv/Architecture.cc

@@ -17,7 +17,25 @@ Architecture::Architecture(kernel::Linux& kernel, ryml::ConstNodeRef config)
   // TODO set fcsr accordingly when Zicsr extension supported
   fesetround(FE_TONEAREST);
 
-  cs_err n = cs_open(CS_ARCH_RISCV, CS_MODE_RISCV64, &capstoneHandle_);
+  cs_err n;
+
+  // Check whether compressed instructions in use. Initialise variables and
+  // Capstone accordingly
+  if (config["Core"]["Compressed"].as<bool>()) {
+    addressAlignmentMask_ = constantsPool::addressAlignMaskCompressed;
+    minInsnLength_ = constantsPool::minInstWidthBytesCompressed;
+
+    n = cs_open(CS_ARCH_RISCV,
+                static_cast<cs_mode>(CS_MODE_RISCV64 | CS_MODE_RISCVC),
+                &capstoneHandle_);
+  } else {
+    addressAlignmentMask_ = constantsPool::addressAlignMask;
+    minInsnLength_ = constantsPool::minInstWidthBytes;
+
+    n = cs_open(CS_ARCH_RISCV, static_cast<cs_mode>(CS_MODE_RISCV64),
+                &capstoneHandle_);
+  }
+
   if (n != CS_ERR_OK) {
     std::cerr << "[SimEng:Architecture] Could not create capstone handle due "
                  "to error "
@@ -141,7 +159,8 @@ uint8_t Architecture::predecode(const void* ptr, uint16_t bytesAvailable,
                                 uint64_t instructionAddress,
                                 MacroOp& output) const {
   // Check that instruction address is 4-byte aligned as required by RISC-V
-  if (instructionAddress & 0x3) {
+  // 2-byte when Compressed extension is supported
+  if (instructionAddress & addressAlignmentMask_) {
     // Consume 1-byte and raise a misaligned PC exception
     auto metadata = InstructionMetadata((uint8_t*)ptr, 1);
     metadataCache_.emplace_front(metadata);
@@ -154,31 +173,65 @@ uint8_t Architecture::predecode(const void* ptr, uint16_t bytesAvailable,
     return 1;
   }
 
-  assert(bytesAvailable >= 4 &&
-         "Fewer than 4 bytes supplied to RISC-V decoder");
-
-  // Dereference the instruction pointer to obtain the instruction word
-  uint32_t insn;
-  memcpy(&insn, ptr, 4);
+  assert(bytesAvailable >= minInsnLength_ &&
+         "Fewer than bytes limit supplied to RISC-V decoder");
+
+  // Get the first byte
+  uint8_t firstByte = ((uint8_t*)ptr)[0];
+
+  uint32_t insnEncoding = 0;
+  size_t insnSize = 4;
+
+  // Predecode bytes to determine whether we have a compressed instruction.
+  // This will allow continuation if a compressed instruction is in the last 2
+  // bytes of a fetch block, but will request more data if only half of a
+  // non-compressed instruction is present
+
+  // Check the 2 least significant bits as these determine instruction length
+  if ((firstByte & 0b11) != 0b11) {
+    // 2 byte - compressed
+    // Only use relevant bytes
+    // Dereference the instruction pointer to obtain the instruction word
+    memcpy(&insnEncoding, ptr, 2);
+    insnSize = 2;
+  } else {
+    // 4 byte
+    if (bytesAvailable < 4) {
+      // Not enough bytes available, bail
+      return 0;
+    }
+    // Dereference the instruction pointer to obtain the instruction word
+    memcpy(&insnEncoding, ptr, 4);
+  }
 
   // Try to find the decoding in the decode cache
-  auto iter = decodeCache_.find(insn);
+  auto iter = decodeCache_.find(insnEncoding);
   if (iter == decodeCache_.end()) {
     // No decoding present. Generate a fresh decoding, and add to cache
-    cs_insn rawInsn;
+    // Calloc memory to ensure rawInsn is initialised with zeros. Errors can
+    // occur otherwise as Capstone doesn't update variables for invalid
+    // instructions
+    cs_insn* rawInsnPointer = (cs_insn*)calloc(1, sizeof(cs_insn));
+    cs_insn rawInsn = *rawInsnPointer;
+    assert(rawInsn.size == 0 && "rawInsn not initialised correctly");
+
     cs_detail rawDetail;
     rawInsn.detail = &rawDetail;
+    // Size requires initialisation in case of capstone failure which won't
+    // update this value
+    rawInsn.size = insnSize;
 
-    size_t size = 4;
     uint64_t address = 0;
 
     const uint8_t* encoding = reinterpret_cast<const uint8_t*>(ptr);
 
-    bool success =
-        cs_disasm_iter(capstoneHandle_, &encoding, &size, &address, &rawInsn);
+    bool success = cs_disasm_iter(capstoneHandle_, &encoding, &insnSize,
+                                  &address, &rawInsn);
+
+    auto metadata = success ? InstructionMetadata(rawInsn)
+                            : InstructionMetadata(encoding, rawInsn.size);
 
-    auto metadata =
-        success ? InstructionMetadata(rawInsn) : InstructionMetadata(encoding);
+    free(rawInsnPointer);
 
     // Cache the metadata
     metadataCache_.push_front(metadata);
@@ -187,10 +240,16 @@ uint8_t Architecture::predecode(const void* ptr, uint16_t bytesAvailable,
     Instruction newInsn(*this, metadataCache_.front());
     // Set execution information for this instruction
     newInsn.setExecutionInfo(getExecutionInfo(newInsn));
+
     // Cache the instruction
-    iter = decodeCache_.insert({insn, newInsn}).first;
+    iter = decodeCache_.insert({insnEncoding, newInsn}).first;
   }
 
+  assert(((insnEncoding & 0b11) != 0b11
+              ? iter->second.getMetadata().getInsnLength() == 2
+              : iter->second.getMetadata().getInsnLength() == 4) &&
+         "Predicted number of bytes don't match disassembled number of bytes");
+
   output.resize(1);
   auto& uop = output[0];
 
@@ -199,7 +258,7 @@ uint8_t Architecture::predecode(const void* ptr, uint16_t bytesAvailable,
 
   uop->setInstructionAddress(instructionAddress);
 
-  return 4;
+  return iter->second.getMetadata().getInsnLength();
 }
 
 int32_t Architecture::getSystemRegisterTag(uint16_t reg) const {
@@ -231,6 +290,8 @@ ProcessStateChange Architecture::getInitialState() const {
 
 uint8_t Architecture::getMaxInstructionSize() const { return 4; }
 
+uint8_t Architecture::getMinInstructionSize() const { return minInsnLength_; }
+
 void Architecture::updateSystemTimerRegisters(RegisterFileSet* regFile,
                                               const uint64_t iterations) const {
   regFile->set(cycleSystemReg_, iterations);

src/lib/arch/riscv/ExceptionHandler.cc

@@ -909,9 +909,10 @@ void ExceptionHandler::printException(const Instruction& insn) const {
             << insn.getInstructionAddress() << ": ";
 
   auto& metadata = insn.getMetadata();
-  for (uint8_t byte : metadata.encoding) {
+  for (uint8_t byteIndex = 0; byteIndex < metadata.getInsnLength();
+       byteIndex++) {
     std::cout << std::setfill('0') << std::setw(2)
-              << static_cast<unsigned int>(byte) << " ";
+              << static_cast<unsigned int>(metadata.encoding[byteIndex]) << " ";
   }
   std::cout << std::dec << "    ";
   if (exception == InstructionException::EncodingUnallocated) {