Architecture Class cleanup

src/include/simeng/Instruction.hh

@@ -13,6 +13,19 @@ using InstructionException = short;
 
 namespace simeng {
 
+/** A struct holding user-defined execution information for an
+ * instruction. */
+struct ExecutionInfo {
+  /** The latency for the instruction. */
+  uint16_t latency = 1;
+
+  /** The execution throughput for the instruction. */
+  uint16_t stallCycles = 1;
+
+  /** The ports that support the instruction. */
+  std::vector<uint16_t> ports = {};
+};
+
 /** An abstract instruction definition.
  * Each supported ISA should provide a derived implementation of this class. */
 class Instruction {

src/include/simeng/arch/Architecture.hh

@@ -7,6 +7,7 @@
 #include "simeng/Core.hh"
 #include "simeng/Instruction.hh"
 #include "simeng/MemoryInterface.hh"
+#include "simeng/kernel/Linux.hh"
 
 namespace simeng {
 
@@ -59,6 +60,8 @@ class ExceptionHandler {
  * ISA should provide a derived implementation of this class. */
 class Architecture {
  public:
+  Architecture(kernel::Linux& kernel) : linux_(kernel) {}
+
   virtual ~Architecture(){};
 
   /** Attempt to pre-decode from `bytesAvailable` bytes of instruction memory.
@@ -90,6 +93,24 @@ class Architecture {
   /** Updates System registers of any system-based timers. */
   virtual void updateSystemTimerRegisters(RegisterFileSet* regFile,
                                           const uint64_t iterations) const = 0;
+
+ protected:
+  /** A Capstone decoding library handle, for decoding instructions. */
+  csh capstoneHandle_;
+
+  /** A reference to a Linux kernel object to forward syscalls to. */
+  kernel::Linux& linux_;
+
+  /** A mapping from system register encoding to a zero-indexed tag. */
+  std::unordered_map<uint16_t, uint16_t> systemRegisterMap_;
+
+  /** A map to hold the relationship between instruction groups and
+   * user-defined execution information. */
+  std::unordered_map<uint16_t, ExecutionInfo> groupExecutionInfo_;
+
+  /** A map to hold the relationship between instruction opcode and
+   * user-defined execution information. */
+  std::unordered_map<uint16_t, ExecutionInfo> opcodeExecutionInfo_;
 };
 
 }  // namespace arch

src/include/simeng/arch/aarch64/Architecture.hh

@@ -7,7 +7,6 @@
 #include "simeng/arch/Architecture.hh"
 #include "simeng/arch/aarch64/ExceptionHandler.hh"
 #include "simeng/arch/aarch64/MicroDecoder.hh"
-#include "simeng/kernel/Linux.hh"
 
 using csh = size_t;
 
@@ -20,7 +19,9 @@ class Architecture : public arch::Architecture {
  public:
   Architecture(kernel::Linux& kernel,
                ryml::ConstNodeRef config = config::SimInfo::getConfig());
+
   ~Architecture();
+
   /** Pre-decode instruction memory into a macro-op of `Instruction`
    * instances. Returns the number of bytes consumed to produce it (always 4),
    * and writes into the supplied macro-op vector. */
@@ -46,13 +47,6 @@ class Architecture : public arch::Architecture {
   /** Returns the maximum size of a valid instruction in bytes. */
   uint8_t getMaxInstructionSize() const override;
 
-  /** Returns the current vector length set by the provided configuration. */
-  uint64_t getVectorLength() const;
-
-  /** Returns the current streaming vector length set by the provided
-   * configuration. */
-  uint64_t getStreamingVectorLength() const;
-
   /** Updates System registers of any system-based timers. */
   void updateSystemTimerRegisters(RegisterFileSet* regFile,
                                   const uint64_t iterations) const override;
@@ -61,7 +55,14 @@ class Architecture : public arch::Architecture {
    * opcode-based override has been defined for the latency and/or
    * port information, return that instead of the group-defined execution
    * information. */
-  ExecutionInfo getExecutionInfo(Instruction& insn) const;
+  virtual ExecutionInfo getExecutionInfo(const Instruction& insn) const;
+
+  /** Returns the current vector length set by the provided configuration. */
+  uint64_t getVectorLength() const;
+
+  /** Returns the current streaming vector length set by the provided
+   * configuration. */
+  uint64_t getStreamingVectorLength() const;
 
   /** Returns the current value of SVCRval_. */
   uint64_t getSVCRval() const;
@@ -73,31 +74,12 @@ class Architecture : public arch::Architecture {
   /** A decoding cache, mapping an instruction word to a previously decoded
    * instruction. Instructions are added to the cache as they're decoded, to
    * reduce the overhead of future decoding. */
-  static std::unordered_map<uint32_t, Instruction> decodeCache_;
+  mutable std::unordered_map<uint32_t, Instruction> decodeCache_;
+
   /** A decoding metadata cache, mapping an instruction word to a previously
    * decoded instruction metadata bundle. Metadata is added to the cache as it's
    * decoded, to reduce the overhead of future decoding. */
-  static std::forward_list<InstructionMetadata> metadataCache_;
-
-  /** A copy of the value of the SVCR system register. */
-  static uint64_t SVCRval_;
-
-  /** A mapping from system register encoding to a zero-indexed tag. */
-  std::unordered_map<uint16_t, uint16_t> systemRegisterMap_;
-
-  /** A map to hold the relationship between aarch64 instruction groups and
-   * user-defined execution information. */
-  std::unordered_map<uint16_t, ExecutionInfo> groupExecutionInfo_;
-
-  /** A map to hold the relationship between aarch64 instruction opcode and
-   * user-defined execution information. */
-  std::unordered_map<uint16_t, ExecutionInfo> opcodeExecutionInfo_;
-
-  /** A Capstone decoding library handle, for decoding instructions. */
-  csh capstoneHandle_;
-
-  /** A reference to a Linux kernel object to forward syscalls to. */
-  kernel::Linux& linux_;
+  mutable std::forward_list<InstructionMetadata> metadataCache_;
 
   /** A reference to a micro decoder object to split macro operations. */
   std::unique_ptr<MicroDecoder> microDecoder_;
@@ -108,6 +90,9 @@ class Architecture : public arch::Architecture {
   /** The streaming vector length used by the SME extension in bits. */
   uint64_t SVL_;
 
+  /** A copy of the value of the SVCR system register. */
+  mutable uint64_t SVCRval_ = 0;
+
   /** System Register of Virtual Counter Timer. */
   simeng::Register VCTreg_;
 

src/include/simeng/arch/aarch64/Instruction.hh

@@ -176,19 +176,6 @@ const uint8_t MATRIX = 5;
 const Register ZERO_REGISTER = {GENERAL, (uint16_t)-1};
 }  // namespace RegisterType
 
-/** A struct holding user-defined execution information for a aarch64
- * instruction. */
-struct ExecutionInfo {
-  /** The latency for the instruction. */
-  uint16_t latency = 1;
-
-  /** The execution throughput for the instruction. */
-  uint16_t stallCycles = 1;
-
-  /** The ports that support the instruction. */
-  std::vector<uint16_t> ports = {};
-};
-
 /** The various exceptions that can be raised by an individual instruction. */
 enum class InstructionException {
   None = 0,

src/include/simeng/arch/riscv/Architecture.hh

@@ -6,7 +6,6 @@
 #include "simeng/arch/Architecture.hh"
 #include "simeng/arch/riscv/ExceptionHandler.hh"
 #include "simeng/arch/riscv/Instruction.hh"
-#include "simeng/kernel/Linux.hh"
 
 using csh = size_t;
 
@@ -19,7 +18,9 @@ class Architecture : public arch::Architecture {
  public:
   Architecture(kernel::Linux& kernel,
                ryml::ConstNodeRef config = config::SimInfo::getConfig());
+
   ~Architecture();
+
   /** Pre-decode instruction memory into a macro-op of `Instruction`
    * instances. Returns the number of bytes consumed to produce it (always 4),
    * and writes into the supplied macro-op vector. */
@@ -49,37 +50,21 @@ class Architecture : public arch::Architecture {
                                   const uint64_t iterations) const override;
 
  private:
-  /** Retrieve an executionInfo object for the requested instruction. If a
+  /** Retrieve an ExecutionInfo object for the requested instruction. If a
    * opcode-based override has been defined for the latency and/or
    * port information, return that instead of the group-defined execution
    * information. */
-  executionInfo getExecutionInfo(Instruction& insn) const;
+  ExecutionInfo getExecutionInfo(const Instruction& insn) const;
 
   /** A decoding cache, mapping an instruction word to a previously decoded
    * instruction. Instructions are added to the cache as they're decoded, to
    * reduce the overhead of future decoding. */
-  static std::unordered_map<uint32_t, Instruction> decodeCache_;
+  mutable std::unordered_map<uint32_t, Instruction> decodeCache_;
+
   /** A decoding metadata cache, mapping an instruction word to a previously
    * decoded instruction metadata bundle. Metadata is added to the cache as it's
    * decoded, to reduce the overhead of future decoding. */
-  static std::forward_list<InstructionMetadata> metadataCache_;
-
-  /** A mapping from system register encoding to a zero-indexed tag. */
-  std::unordered_map<uint16_t, uint16_t> systemRegisterMap_;
-
-  /** A map to hold the relationship between aarch64 instruction groups and
-   * user-defined execution information. */
-  std::unordered_map<uint16_t, executionInfo> groupExecutionInfo_;
-
-  /** A map to hold the relationship between aarch64 instruction opcode and
-   * user-defined execution information. */
-  std::unordered_map<uint16_t, executionInfo> opcodeExecutionInfo_;
-
-  /** A Capstone decoding library handle, for decoding instructions. */
-  csh capstoneHandle_;
-
-  /** A reference to a Linux kernel object to forward syscalls to. */
-  kernel::Linux& linux_;
+  mutable std::forward_list<InstructionMetadata> metadataCache_;
 
   /** System Register of Processor Cycle Counter. */
   simeng::Register cycleSystemReg_;

src/include/simeng/arch/riscv/Instruction.hh

@@ -28,19 +28,6 @@ const uint8_t SYSTEM = 2;
 const Register ZERO_REGISTER = {GENERAL, (uint16_t)0};
 }  // namespace RegisterType
 
-/** A struct holding user-defined execution information for a aarch64
- * instruction. */
-struct executionInfo {
-  /** The latency for the instruction. */
-  uint16_t latency = 1;
-
-  /** The execution throughput for the instruction. */
-  uint16_t stallCycles = 1;
-
-  /** The ports that support the instruction. */
-  std::vector<uint16_t> ports = {};
-};
-
 /** The various exceptions that can be raised by an individual instruction. */
 enum class InstructionException {
   None = 0,
@@ -158,7 +145,7 @@ class Instruction : public simeng::Instruction {
 
   /** Set this instruction's execution information including it's execution
    * latency and throughput, and the set of ports which support it. */
-  void setExecutionInfo(const executionInfo& info);
+  void setExecutionInfo(const ExecutionInfo& info);
 
   /** Get this instruction's supported set of ports. */
   const std::vector<uint16_t>& getSupportedPorts() override;