arch/riscv: replace atomic operations to AMO #12232
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RISC-V provided fetch-and-op style atomic primitives as they scale to highly parallel systems better than LR/SC or CAS. A simple microarchitecture can implement AMOs using the LR/SC primitives, provided the implementation can guarantee the AMO eventually completes. More complex implementations might also implement AMOs at memory controllers, and can optimize away fetching the original value when the destination is x0. Signed-off-by: chao an <anchao@lixiang.com> Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
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@anchao |
xiaoxiang781216
approved these changes
Apr 25, 2024
masayuki2009
approved these changes
Apr 25, 2024
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Summary
arch/riscv: replace atomic operations to AMO
RISC-V provided fetch-and-op style atomic primitives as they scale to highly parallel systems better than LR/SC or CAS. A simple microarchitecture can implement AMOs using the LR/SC primitives, provided the implementation can guarantee the AMO eventually completes. More complex implementations might also implement AMOs at memory controllers, and can optimize away fetching the original value when the destination is x0.
https://github.com/riscv/riscv-isa-manual/blob/main/src/a-st-ext.adoc
Signed-off-by: chao an anchao@lixiang.com
Co-authored-by: Petro Karashchenko petro.karashchenko@gmail.com
Impact
#6569
Closes #6569
N/A
Testing
rv-virt/smp64 rv-virt/smp