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Add max width #90

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Merged
mmcloughlin merged 1 commit into from
Feb 14, 2024
Merged

Add max width #90

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3 changes: 3 additions & 0 deletions cranelift/isle/veri/veri_engine/src/lib.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,9 @@ pub mod verify;

pub const REG_WIDTH: usize = 64;

// Use a distinct with as the maximum width any value should have within type inference
pub const MAX_WIDTH: usize = 4*REG_WIDTH;
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@mmcloughlin mmcloughlin Feb 14, 2024

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Is it worth limiting this to 2*REG_WIDTH at this point? Or do you think the width should have limited impact on solver performance?


pub const FLAGS_WIDTH: usize = 4;

pub const WIDTHS: [usize; 4] = [8, 16, 32, 64];
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12 changes: 6 additions & 6 deletions cranelift/isle/veri/veri_engine/src/solver.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@ use encoded_ops::clz;
use encoded_ops::rev;
use encoded_ops::subs;

use crate::REG_WIDTH;
use crate::MAX_WIDTH;

pub struct SolverCtx {
smt: easy_smt::Context,
Expand Down Expand Up @@ -1678,7 +1678,7 @@ pub fn run_solver(
dynwidths: true,
onlywidths: false,
tyctx: rule_sem.tyctx.clone(),
bitwidth: REG_WIDTH,
bitwidth: MAX_WIDTH,
var_map: HashMap::new(),
width_vars: HashMap::new(),
width_assumptions: vec![],
Expand Down Expand Up @@ -1882,7 +1882,7 @@ pub fn run_solver_with_static_widths(
dynwidths: false,
onlywidths: false,
tyctx: tyctx.clone(),
bitwidth: REG_WIDTH,
bitwidth: MAX_WIDTH,
var_map: HashMap::new(),
width_vars: HashMap::new(),
width_assumptions: vec![],
Expand Down Expand Up @@ -1918,13 +1918,13 @@ pub fn run_solver_with_static_widths(
(None, None) => {
println!(
"Width of relevant bits of LHS and RHS unknown, using full register bitwidth: {}",
REG_WIDTH
MAX_WIDTH
);
REG_WIDTH
MAX_WIDTH
}
};

let (lhs_care_bits, rhs_care_bits) = if width == REG_WIDTH {
let (lhs_care_bits, rhs_care_bits) = if width == MAX_WIDTH {
(lhs, rhs)
} else {
(
Expand Down