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Feature: JTAG TAP RISC-V prep#1131

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esden merged 13 commits into
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feature/jtag-tap-riscv-prep
Jul 30, 2022
Merged

Feature: JTAG TAP RISC-V prep#1131
esden merged 13 commits into
mainfrom
feature/jtag-tap-riscv-prep

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@dragonmux
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This PR finishes the cleanup of the JTAG TAP code and adds a couple of new things needed for supporting buggy targets and RISC-V debugging.

The two new items this introduces are:

  • Support for running the JTAG clock for a number of cycles with fixed TDI and TMS pin values
  • Support for skipping or dwelling in the JTAG Idle state as required

This should mark the last of the RISC-V support setup.

@dragonmux dragonmux added the Enhancement General project improvement label Jul 25, 2022
@dragonmux dragonmux added this to the v1.9 release milestone Jul 25, 2022
@dragonmux dragonmux requested a review from esden July 25, 2022 10:18
@dragonmux dragonmux force-pushed the feature/jtag-tap-riscv-prep branch 2 times, most recently from b088b99 to aa2d44f Compare July 25, 2022 17:05
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LGTM

@esden esden merged commit 1ea9641 into main Jul 30, 2022
@dragonmux dragonmux deleted the feature/jtag-tap-riscv-prep branch July 30, 2022 23:29
@dragonmux dragonmux mentioned this pull request Nov 18, 2022
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@dragonmux dragonmux mentioned this pull request Feb 12, 2023
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2 participants