Add a third register class

[afonso360]

👋 Hey,

For machines with completely separate vector registers it is useful to have a separate third register class. It looks like we now have encoding space to support that.

I've run all 5 fuzzers for about a couple of hours, and nothing showed up.

Fixes: #47

[cfallin]

This looks great -- thanks!

Once this merges, I'm happy to r+ another PR to bump the version. I think this is a semver break because we added an enum item to RegClass, so that'd be 0.8.0. I'm happy to cargo publish then and we can pull it into Cranelift.

(Incidentally, on the Cranelift side we'll need to bump this constant to allow representing Vec-class pregs in instructions. The verbiage there is a bit out-of-date as the preg-as-vreg index range isn't "pinned" per se, just an encoding; but we can refine in a separate CL PR!)

[cfallin]

@afonso360 one thing I realized when discussing another regalloc-related question: the PRegSet is currently a bitset using one u128, so it can represent two classes with maximum 64 regs each (128 total) but with three classes we now need 192 bits. This would manifest as an error when computing clobbers as soon as you actually tried to use the new class. Would you mind extending it too (probably with another u128 so we cover the eventual four possible classes with 256 bits)? Thanks!