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These were previous displayed as a Use with a very large vreg number.
cfallin
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Apr 30, 2023
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Thanks! Just a few requests below but basically looks good.
src/lib.rs
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| debug_assert!(reg.index() < 256); | ||
| let bit = reg.index() & 127; | ||
| let index = reg.index() >> 7; | ||
| self.bits[index] & 1u128 << bit != 0 |
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This is correct wrt operator precedence but it causes me to pause for a moment -- for easier mental parsing, could we add parens around 1u128 << bit ?
| let index = reg.index() >> 7; | ||
| let mut out = self; | ||
| out.bits[index] |= 1u128 << bit; | ||
| out |
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Now that this logic has become slightly more complex, perhaps we could delegate to add with something like
let mut out = self;
out.add(reg);
out
?
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I tried that at first, but it's not possible since with is a const fn. add can't be made const because it uses &mut self.
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| #[inline(always)] | ||
| pub const fn class(self) -> RegClass { | ||
| match self.bits & (0b11 << Self::MAX_BITS) { | ||
| match (self.bits >> Self::MAX_BITS) & 0b11 { |
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And, yikes, thanks for catching this -- sorry I missed it in review!
Amanieu
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This contains the bug fixes from bytecodealliance#129.
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This contains the bug fixes from #129.
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This PR fixes 3 issues:
PReg::classwas broken by Add a third register class #126.PRegSetneeds more than 128 bits for 3 register classes.impl Display for Operandwas incorrect for fixed-non-allocatable operands.