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Constify backends #1502

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05d3cc5
Constify registerinfo.py output
rth7680 May 30, 2019
c822a17
Constify instrinfo-arch.py output
rth7680 May 30, 2019
35a83ea
Constify systemregister.py output
rth7680 May 30, 2019
906c820
Constify the AArch64 backend
rth7680 May 28, 2019
7d0f810
Constify the ARM backend
rth7680 Oct 14, 2019
58e27d9
Constify the EVM backend
rth7680 May 28, 2019
625a50b
Constify M680X backend
rth7680 May 28, 2019
179272b
Constify M68K backend
rth7680 May 28, 2019
8821b5c
Constify the Mips backend
rth7680 May 28, 2019
c94b489
Constify the PowerPC backend
rth7680 Oct 14, 2019
17fd883
Constify the Sparc backend
rth7680 May 28, 2019
259c0e7
Constify the TMS320C64x backend
rth7680 May 28, 2019
7539135
Constify the X86 backend
rth7680 May 28, 2019
e177996
Constify the XCore backend
rth7680 May 28, 2019
443734c
Constify the MOS65XX backend
rth7680 Oct 14, 2019
735a673
Constify the SystemZ backend
rth7680 Oct 14, 2019
74a8f69
Constify the WASM backend
rth7680 Oct 14, 2019
5c16b63
Constify the BPF backend
rth7680 Oct 14, 2019
b291783
Constify cs.c
rth7680 Oct 14, 2019
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832 changes: 416 additions & 416 deletions arch/AArch64/AArch64GenInstrInfo.inc
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4 changes: 2 additions & 2 deletions arch/AArch64/AArch64GenRegisterInfo.inc
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Expand Up @@ -1032,7 +1032,7 @@ static const uint16_t AArch64SubRegIdxLists[] = {
/* 181 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 23, 64, 61, 63, 62, 60, 65, 24, 58, 55, 57, 56, 54, 59, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 0,
};

static MCRegisterDesc AArch64RegDesc[] = {
static const MCRegisterDesc AArch64RegDesc[] = {
{ 3, 0, 0, 0, 0, 0 },
{ 2489, 8, 8, 4, 20465, 0 },
{ 2482, 878, 405, 5, 20465, 27 },
Expand Down Expand Up @@ -2498,7 +2498,7 @@ static MCRegisterDesc AArch64RegDesc[] = {
};


static MCRegisterClass AArch64MCRegisterClasses[] = {
static const MCRegisterClass AArch64MCRegisterClasses[] = {
{ FPR8, FPR8Bits, sizeof(FPR8Bits) },
{ FPR16, FPR16Bits, sizeof(FPR16Bits) },
{ PPR, PPRBits, sizeof(PPRBits) },
Expand Down
2 changes: 1 addition & 1 deletion arch/AArch64/AArch64InstPrinter.c
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Expand Up @@ -54,7 +54,7 @@ static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx,
static cs_ac_type get_op_access(cs_struct *h, unsigned int id, unsigned int index)
{
#ifndef CAPSTONE_DIET
uint8_t *arr = AArch64_get_op_access(h, id);
const uint8_t *arr = AArch64_get_op_access(h, id);

if (arr[index] == CS_AC_IGNORE)
return 0;
Expand Down
8 changes: 4 additions & 4 deletions arch/AArch64/AArch64Mapping.c
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Expand Up @@ -15,7 +15,7 @@

#ifndef CAPSTONE_DIET
// NOTE: this reg_name_maps[] reflects the order of registers in arm64_reg
static const char *reg_name_maps[] = {
static const char * const reg_name_maps[] = {
NULL, /* ARM64_REG_INVALID */

"ffr",
Expand Down Expand Up @@ -389,7 +389,7 @@ void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
}
}

static const char *insn_name_maps[] = {
static const char * const insn_name_maps[] = {
NULL, // ARM64_INS_INVALID
#include "AArch64MappingInsnName.inc"
"sbfiz",
Expand Down Expand Up @@ -523,7 +523,7 @@ typedef struct insn_op {
uint8_t access[5];
} insn_op;

static insn_op insn_ops[] = {
static const insn_op insn_ops[] = {
{
/* NULL item */
0, { 0 }
Expand All @@ -533,7 +533,7 @@ static insn_op insn_ops[] = {
};

// given internal insn id, return operand access info
uint8_t *AArch64_get_op_access(cs_struct *h, unsigned int id)
const uint8_t *AArch64_get_op_access(cs_struct *h, unsigned int id)
{
int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
if (i != 0) {
Expand Down
2 changes: 1 addition & 1 deletion arch/AArch64/AArch64Mapping.h
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Expand Up @@ -32,7 +32,7 @@ void arm64_op_addFP(MCInst *MI, float fp);

void arm64_op_addImm(MCInst *MI, int64_t imm);

uint8_t *AArch64_get_op_access(cs_struct *h, unsigned int id);
const uint8_t *AArch64_get_op_access(cs_struct *h, unsigned int id);

void AArch64_reg_access(const cs_insn *insn,
cs_regs regs_read, uint8_t *regs_read_count,
Expand Down
12 changes: 6 additions & 6 deletions arch/ARM/ARMBaseInfo.h
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Expand Up @@ -443,30 +443,30 @@ enum TraceSyncBOpt {
CSYNC = 0
};

MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding);
MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12);
const MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding);
const MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12);

// returns APSR with _<bits> qualifier.
// Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier
static inline MClassSysReg *lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm)
static inline const MClassSysReg *lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm)
{
return lookupMClassSysRegByM2M3Encoding8((1<<9) | (SYSm & 0xFF));
}

static inline MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm)
static inline const MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm)
{
return lookupMClassSysRegByM2M3Encoding8((1<<8) | (SYSm & 0xFF));
}

// returns true if TestFeatures are all present in FeaturesRequired
static inline bool MClassSysReg_isInRequiredFeatures(MClassSysReg *TheReg, int TestFeatures)
static inline bool MClassSysReg_isInRequiredFeatures(const MClassSysReg *TheReg, int TestFeatures)
{
return (TheReg->FeaturesRequired[0] == TestFeatures || TheReg->FeaturesRequired[1] == TestFeatures);
}

// lookup system register using 12-bit SYSm value.
// Note: the search is uniqued using M1 mask
static inline MClassSysReg *lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm)
static inline const MClassSysReg *lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm)
{
return lookupMClassSysRegByM1Encoding12(SYSm);
}
Expand Down
836 changes: 418 additions & 418 deletions arch/ARM/ARMGenInstrInfo.inc
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4 changes: 2 additions & 2 deletions arch/ARM/ARMGenRegisterInfo.inc
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Expand Up @@ -875,7 +875,7 @@ static const uint16_t ARMSubRegIdxLists[] = {
/* 474 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 29, 30, 8, 31, 32, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
};

static MCRegisterDesc ARMRegDesc[] = {
static const MCRegisterDesc ARMRegDesc[] = {
{ 12, 0, 0, 0, 0, 0 },
{ 1235, 16, 16, 2, 66945, 0 },
{ 1268, 16, 16, 2, 66945, 0 },
Expand Down Expand Up @@ -1993,7 +1993,7 @@ static MCRegisterDesc ARMRegDesc[] = {
};


static MCRegisterClass ARMMCRegisterClasses[] = {
static const MCRegisterClass ARMMCRegisterClasses[] = {
{ HPR, HPRBits, sizeof(HPRBits) },
{ SPR, SPRBits, sizeof(SPRBits) },
{ GPR, GPRBits, sizeof(GPRBits) },
Expand Down
10 changes: 5 additions & 5 deletions arch/ARM/ARMGenSystemRegister.inc
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Expand Up @@ -46,7 +46,7 @@ enum BankedRegValues {
spsr_und = 32,
};

static MClassSysReg MClassSysRegsList[] = {
static const MClassSysReg MClassSysRegsList[] = {
{ "apsr_g", ARM_SYSREG_APSR_G, 0x400, 0x0, 0x400, {ARM_FeatureDSP} }, // 0
{ "apsr_nzcvqg", ARM_SYSREG_APSR_NZCVQG, 0xC00, 0x300, 0xC00, {ARM_FeatureDSP} }, // 1
{ "iapsr_g", ARM_SYSREG_IAPSR_G, 0x401, 0x1, 0x401, {ARM_FeatureDSP} }, // 2
Expand Down Expand Up @@ -86,7 +86,7 @@ static MClassSysReg MClassSysRegsList[] = {
{ "sp_ns", ARM_SYSREG_SP_NS, 0x898, 0x198, 0x898, {ARM_Feature8MSecExt} }, // 36
};

static BankedReg BankedRegsList[] = {
static const BankedReg BankedRegsList[] = {
{ "r8_usr", ARM_SYSREG_R8_USR, 0x0 }, // 0
{ "r9_usr", ARM_SYSREG_R9_USR, 0x1 }, // 1
{ "r10_usr", ARM_SYSREG_R10_USR, 0x2 }, // 2
Expand Down Expand Up @@ -122,7 +122,7 @@ static BankedReg BankedRegsList[] = {
{ "spsr_hyp", ARM_SYSREG_SPSR_HYP, 0x3E }, // 32
};

MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding)
const MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding)
{
unsigned int i;
static const struct IndexType Index[] = {
Expand Down Expand Up @@ -172,7 +172,7 @@ MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding)
return &MClassSysRegsList[Index[i].index];
}

MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t encoding)
const MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t encoding)
{
unsigned int i;
static const struct IndexType Index[] = {
Expand Down Expand Up @@ -222,7 +222,7 @@ MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t encoding)
return &MClassSysRegsList[Index[i].index];
}

BankedReg *lookupBankedRegByEncoding(uint8_t encoding)
const BankedReg *lookupBankedRegByEncoding(uint8_t encoding)
{
unsigned int i;
static const struct IndexType Index[] = {
Expand Down
6 changes: 3 additions & 3 deletions arch/ARM/ARMInstPrinter.c
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Expand Up @@ -131,7 +131,7 @@ static void printAddrMode5FP16Operand(MCInst *MI, unsigned OpNum, SStream *O, bo
// copy & normalize access info
static uint8_t get_op_access(cs_struct *h, unsigned int id, unsigned int index)
{
uint8_t *arr = ARM_get_op_access(h, id);
const uint8_t *arr = ARM_get_op_access(h, id);

if (!arr || arr[index] == CS_AC_IGNORE)
return 0;
Expand Down Expand Up @@ -1734,7 +1734,7 @@ static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O)
unsigned reg;

if (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass)) {
MClassSysReg *TheReg;
const MClassSysReg *TheReg;
unsigned SYSm = (unsigned)MCOperand_getImm(Op) & 0xFFF; // 12-bit SYMm
unsigned Opcode = MCInst_getOpcode(MI);

Expand Down Expand Up @@ -1827,7 +1827,7 @@ static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O)
static void printBankedRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
uint32_t Banked = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
BankedReg *TheReg = lookupBankedRegByEncoding(Banked);
const BankedReg *TheReg = lookupBankedRegByEncoding(Banked);

SStream_concat0(O, TheReg->Name);
ARM_addSysReg(MI, TheReg->sysreg);
Expand Down
6 changes: 3 additions & 3 deletions arch/ARM/ARMMapping.c
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Expand Up @@ -345,7 +345,7 @@ void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
}

#ifndef CAPSTONE_DIET
static const char *insn_name_maps[] = {
static const char * const insn_name_maps[] = {
NULL, // ARM_INS_INVALID
#include "ARMMappingInsnName.inc"
};
Expand Down Expand Up @@ -475,7 +475,7 @@ typedef struct insn_op {
uint8_t access[7];
} insn_op;

static insn_op insn_ops[] = {
static const insn_op insn_ops[] = {
{
// NULL item
{ 0 }
Expand All @@ -485,7 +485,7 @@ static insn_op insn_ops[] = {
};

// given internal insn id, return operand access info
uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id)
const uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id)
{
int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
if (i != 0) {
Expand Down
4 changes: 2 additions & 2 deletions arch/ARM/ARMMapping.h
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Expand Up @@ -23,7 +23,7 @@ bool ARM_rel_branch(cs_struct *h, unsigned int insn_id);

bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int insn_id);

uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id);
const uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id);

void ARM_reg_access(const cs_insn *insn,
cs_regs regs_read, uint8_t *regs_read_count,
Expand All @@ -35,6 +35,6 @@ typedef struct BankedReg {
uint16_t Encoding;
} BankedReg;

BankedReg *lookupBankedRegByEncoding(uint8_t encoding);
const BankedReg *lookupBankedRegByEncoding(uint8_t encoding);

#endif
2 changes: 1 addition & 1 deletion arch/BPF/BPFMapping.c
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Expand Up @@ -137,7 +137,7 @@ const char *BPF_reg_name(csh handle, unsigned int reg)
if (EBPF_MODE(handle)) {
if (reg < BPF_REG_R0 || reg > BPF_REG_R10)
return NULL;
static const char* reg_names[11] = {
static const char reg_names[11][4] = {
"r0", "r1", "r2", "r3", "r4",
"r5", "r6", "r7", "r8", "r9",
"r10"
Expand Down
2 changes: 1 addition & 1 deletion arch/EVM/EVMDisassembler.c
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Expand Up @@ -8,7 +8,7 @@
#include "EVMDisassembler.h"
#include "EVMMapping.h"

static short opcodes[256] = {
static const short opcodes[256] = {
EVM_INS_STOP,
EVM_INS_ADD,
EVM_INS_MUL,
Expand Down
8 changes: 4 additions & 4 deletions arch/EVM/EVMMapping.c
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Expand Up @@ -11,14 +11,14 @@
#include "EVMMapping.h"

#ifndef CAPSTONE_DIET
static cs_evm insns[256] = {
static const cs_evm insns[256] = {
#include "EVMMappingInsn.inc"
};
#endif

// look for @id in @insns, given its size in @max.
// return -1 if not found
static int evm_insn_find(cs_evm *insns, unsigned int max, unsigned int id)
static int evm_insn_find(const cs_evm *insns, unsigned int max, unsigned int id)
{
if (id >= max)
return -1;
Expand All @@ -44,7 +44,7 @@ void EVM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
}

#ifndef CAPSTONE_DIET
static name_map insn_name_maps[256] = {
static const name_map insn_name_maps[256] = {
{ EVM_INS_STOP, "stop" },
{ EVM_INS_ADD, "add" },
{ EVM_INS_MUL, "mul" },
Expand Down Expand Up @@ -317,7 +317,7 @@ const char *EVM_insn_name(csh handle, unsigned int id)
}

#ifndef CAPSTONE_DIET
static name_map group_name_maps[] = {
static const name_map group_name_maps[] = {
// generic groups
{ EVM_GRP_INVALID, NULL },
{ EVM_GRP_JUMP, "jump" },
Expand Down
6 changes: 3 additions & 3 deletions arch/M680X/M680XDisassembler.c
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Expand Up @@ -1399,11 +1399,11 @@ static void indexed09_hdlr(MCInst *MI, m680x_info *info, uint16_t *address)
}


m680x_reg g_idx12_to_reg_ids[4] = {
static const m680x_reg g_idx12_to_reg_ids[4] = {
M680X_REG_X, M680X_REG_Y, M680X_REG_S, M680X_REG_PC,
};

m680x_reg g_or12_to_reg_ids[3] = {
static const m680x_reg g_or12_to_reg_ids[3] = {
M680X_REG_A, M680X_REG_B, M680X_REG_D
};

Expand Down Expand Up @@ -2130,7 +2130,7 @@ static const cpu_tables g_cpu_tables[] = {
},
};

static const char *s_cpu_type[] = {
static const char * const s_cpu_type[] = {
"INVALID", "6301", "6309", "6800", "6801", "6805", "6808",
"6809", "6811", "CPU12", "HCS08",
};
Expand Down
2 changes: 1 addition & 1 deletion arch/M680X/M680XInstPrinter.c
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Expand Up @@ -87,7 +87,7 @@ static const char s_instruction_names[][6] = {
"xgdx", "xgdy",
};

static name_map s_group_names[] = {
static const name_map s_group_names[] = {
{ M680X_GRP_INVALID, "<invalid>" },
{ M680X_GRP_JUMP, "jump" },
{ M680X_GRP_CALL, "call" },
Expand Down
16 changes: 8 additions & 8 deletions arch/M68K/M68KDisassembler.c
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Expand Up @@ -222,38 +222,38 @@ typedef struct {
/* ================================= DATA ================================= */
/* ======================================================================== */

static instruction_struct g_instruction_table[0x10000];
static const instruction_struct g_instruction_table[0x10000];

/* used by ops like asr, ror, addq, etc */
static uint32_t g_3bit_qdata_table[8] = {8, 1, 2, 3, 4, 5, 6, 7};
static const uint32_t g_3bit_qdata_table[8] = {8, 1, 2, 3, 4, 5, 6, 7};

static uint32_t g_5bit_data_table[32] = {
static const uint32_t g_5bit_data_table[32] = {
32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
};

static m68k_insn s_branch_lut[] = {
static const m68k_insn s_branch_lut[] = {
M68K_INS_INVALID, M68K_INS_INVALID, M68K_INS_BHI, M68K_INS_BLS,
M68K_INS_BCC, M68K_INS_BCS, M68K_INS_BNE, M68K_INS_BEQ,
M68K_INS_BVC, M68K_INS_BVS, M68K_INS_BPL, M68K_INS_BMI,
M68K_INS_BGE, M68K_INS_BLT, M68K_INS_BGT, M68K_INS_BLE,
};

static m68k_insn s_dbcc_lut[] = {
static const m68k_insn s_dbcc_lut[] = {
M68K_INS_DBT, M68K_INS_DBF, M68K_INS_DBHI, M68K_INS_DBLS,
M68K_INS_DBCC, M68K_INS_DBCS, M68K_INS_DBNE, M68K_INS_DBEQ,
M68K_INS_DBVC, M68K_INS_DBVS, M68K_INS_DBPL, M68K_INS_DBMI,
M68K_INS_DBGE, M68K_INS_DBLT, M68K_INS_DBGT, M68K_INS_DBLE,
};

static m68k_insn s_scc_lut[] = {
static const m68k_insn s_scc_lut[] = {
M68K_INS_ST, M68K_INS_SF, M68K_INS_SHI, M68K_INS_SLS,
M68K_INS_SCC, M68K_INS_SCS, M68K_INS_SNE, M68K_INS_SEQ,
M68K_INS_SVC, M68K_INS_SVS, M68K_INS_SPL, M68K_INS_SMI,
M68K_INS_SGE, M68K_INS_SLT, M68K_INS_SGT, M68K_INS_SLE,
};

static m68k_insn s_trap_lut[] = {
static const m68k_insn s_trap_lut[] = {
M68K_INS_TRAPT, M68K_INS_TRAPF, M68K_INS_TRAPHI, M68K_INS_TRAPLS,
M68K_INS_TRAPCC, M68K_INS_TRAPCS, M68K_INS_TRAPNE, M68K_INS_TRAPEQ,
M68K_INS_TRAPVC, M68K_INS_TRAPVS, M68K_INS_TRAPPL, M68K_INS_TRAPMI,
Expand Down Expand Up @@ -3379,7 +3379,7 @@ static void d68020_unpk_mm(m68k_info *info)
static int instruction_is_valid(m68k_info *info, const unsigned int word_check)
{
const unsigned int instruction = info->ir;
instruction_struct *i = &g_instruction_table[instruction];
const instruction_struct *i = &g_instruction_table[instruction];

if ( (i->word2_mask && ((word_check & i->word2_mask) != i->word2_match)) ||
(i->instruction == d68000_invalid) ) {
Expand Down
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