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18 changes: 10 additions & 8 deletions bindings/ocaml/ocaml.c
Original file line number Diff line number Diff line change
Expand Up @@ -369,15 +369,15 @@ CAMLprim value _cs_disasm(cs_arch arch, csh handle, const uint8_t * code, size_t
for (i = 0; i < lcount; i++) {
switch(insn[j-1].detail->x86.operands[i].type) {
case X86_OP_REG:
tmp = caml_alloc(5, 1);
tmp = caml_alloc(1, 1);
Store_field(tmp, 0, Val_int(insn[j-1].detail->x86.operands[i].reg));
break;
case X86_OP_IMM:
tmp = caml_alloc(5, 2);
tmp = caml_alloc(1, 2);
Store_field(tmp, 0, Val_int(insn[j-1].detail->x86.operands[i].imm));
break;
case X86_OP_MEM:
tmp = caml_alloc(5, 3);
tmp = caml_alloc(1, 3);
tmp2 = caml_alloc(5, 0);
Store_field(tmp2, 0, Val_int(insn[j-1].detail->x86.operands[i].mem.segment));
Store_field(tmp2, 1, Val_int(insn[j-1].detail->x86.operands[i].mem.base));
Expand All @@ -388,14 +388,16 @@ CAMLprim value _cs_disasm(cs_arch arch, csh handle, const uint8_t * code, size_t
Store_field(tmp, 0, tmp2);
break;
default:
tmp = caml_alloc(1, 0); // X86_OP_INVALID
break;
}
Store_field(tmp, 1, Val_int(insn[j-1].detail->x86.operands[i].size));
Store_field(tmp, 2, Val_int(insn[j-1].detail->x86.operands[i].access));
Store_field(tmp, 3, Val_int(insn[j-1].detail->x86.operands[i].avx_bcast));
Store_field(tmp, 4, Val_int(insn[j-1].detail->x86.operands[i].avx_zero_opmask));
tmp2 = caml_alloc(1, 0);

tmp2 = caml_alloc(5, 0);
Store_field(tmp2, 0, tmp);
Store_field(tmp2, 1, Val_int(insn[j-1].detail->x86.operands[i].size));
Store_field(tmp2, 2, Val_int(insn[j-1].detail->x86.operands[i].access));
Store_field(tmp2, 3, Val_int(insn[j-1].detail->x86.operands[i].avx_bcast));
Store_field(tmp2, 4, Val_int(insn[j-1].detail->x86.operands[i].avx_zero_opmask));
Store_field(array, i, tmp2);
}
} else // empty array
Expand Down
6 changes: 3 additions & 3 deletions bindings/ocaml/test_x86.ml
Original file line number Diff line number Diff line change
Expand Up @@ -30,9 +30,9 @@ let all_tests = [
let print_op handle i op =
( match op.value with
| X86_OP_INVALID _ -> (); (* this would never happens *)
| X86_OP_REG reg -> printf "\t\top[%d]: REG = %s\n" i (cs_reg_name handle reg);
| X86_OP_IMM imm -> printf "\t\top[%d]: IMM = 0x%x\n" i imm;
| X86_OP_MEM mem -> ( printf "\t\top[%d]: MEM\n" i;
| X86_OP_REG reg -> printf "\t\top[%d]: REG = %s [sz=%d]\n" i (cs_reg_name handle reg) op.size;
| X86_OP_IMM imm -> printf "\t\top[%d]: IMM = 0x%x [sz=%d]\n" i imm op.size;
| X86_OP_MEM mem -> ( printf "\t\top[%d]: MEM [sz=%d]\n" i op.size;
if mem.base != 0 then
printf "\t\t\toperands[%u].mem.base: REG = %s\n" i (cs_reg_name handle mem.base);
if mem.index != 0 then
Expand Down