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[Deepin-Kernel-SIG] [Upstream] [linux 6.6-y] Loongarch: Sync some patches from stable #583

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Merged
opsiff merged 2 commits into from
Feb 6, 2025
Merged

[Deepin-Kernel-SIG] [Upstream] [linux 6.6-y] Loongarch: Sync some patches from stable #583

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73861d7
LoongArch: Fix warnings during S3 suspend
chenhuacai Jan 26, 2025
0ec82f4
LoongArch: Change 8 to 14 for LOONGARCH_MAX_{BRP,WRP}
seehearfeel Jan 26, 2025
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4 changes: 2 additions & 2 deletions arch/loongarch/include/asm/hw_breakpoint.h
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Original file line number Diff line number Diff line change
Expand Up @@ -38,8 +38,8 @@ struct arch_hw_breakpoint {
* Limits.
* Changing these will require modifications to the register accessors.
*/
#define LOONGARCH_MAX_BRP 8
#define LOONGARCH_MAX_WRP 8
#define LOONGARCH_MAX_BRP 14
#define LOONGARCH_MAX_WRP 14

/* Virtual debug register bases. */
#define CSR_CFG_ADDR 0
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60 changes: 60 additions & 0 deletions arch/loongarch/include/asm/loongarch.h
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Original file line number Diff line number Diff line change
Expand Up @@ -950,6 +950,36 @@
#define LOONGARCH_CSR_DB7CTRL 0x34a /* data breakpoint 7 control */
#define LOONGARCH_CSR_DB7ASID 0x34b /* data breakpoint 7 asid */

#define LOONGARCH_CSR_DB8ADDR 0x350 /* data breakpoint 8 address */
#define LOONGARCH_CSR_DB8MASK 0x351 /* data breakpoint 8 mask */
#define LOONGARCH_CSR_DB8CTRL 0x352 /* data breakpoint 8 control */
#define LOONGARCH_CSR_DB8ASID 0x353 /* data breakpoint 8 asid */

#define LOONGARCH_CSR_DB9ADDR 0x358 /* data breakpoint 9 address */
#define LOONGARCH_CSR_DB9MASK 0x359 /* data breakpoint 9 mask */
#define LOONGARCH_CSR_DB9CTRL 0x35a /* data breakpoint 9 control */
#define LOONGARCH_CSR_DB9ASID 0x35b /* data breakpoint 9 asid */

#define LOONGARCH_CSR_DB10ADDR 0x360 /* data breakpoint 10 address */
#define LOONGARCH_CSR_DB10MASK 0x361 /* data breakpoint 10 mask */
#define LOONGARCH_CSR_DB10CTRL 0x362 /* data breakpoint 10 control */
#define LOONGARCH_CSR_DB10ASID 0x363 /* data breakpoint 10 asid */

#define LOONGARCH_CSR_DB11ADDR 0x368 /* data breakpoint 11 address */
#define LOONGARCH_CSR_DB11MASK 0x369 /* data breakpoint 11 mask */
#define LOONGARCH_CSR_DB11CTRL 0x36a /* data breakpoint 11 control */
#define LOONGARCH_CSR_DB11ASID 0x36b /* data breakpoint 11 asid */

#define LOONGARCH_CSR_DB12ADDR 0x370 /* data breakpoint 12 address */
#define LOONGARCH_CSR_DB12MASK 0x371 /* data breakpoint 12 mask */
#define LOONGARCH_CSR_DB12CTRL 0x372 /* data breakpoint 12 control */
#define LOONGARCH_CSR_DB12ASID 0x373 /* data breakpoint 12 asid */

#define LOONGARCH_CSR_DB13ADDR 0x378 /* data breakpoint 13 address */
#define LOONGARCH_CSR_DB13MASK 0x379 /* data breakpoint 13 mask */
#define LOONGARCH_CSR_DB13CTRL 0x37a /* data breakpoint 13 control */
#define LOONGARCH_CSR_DB13ASID 0x37b /* data breakpoint 13 asid */

#define LOONGARCH_CSR_FWPC 0x380 /* instruction breakpoint config */
#define LOONGARCH_CSR_FWPS 0x381 /* instruction breakpoint status */

Expand Down Expand Up @@ -993,6 +1023,36 @@
#define LOONGARCH_CSR_IB7CTRL 0x3ca /* inst breakpoint 7 control */
#define LOONGARCH_CSR_IB7ASID 0x3cb /* inst breakpoint 7 asid */

#define LOONGARCH_CSR_IB8ADDR 0x3d0 /* inst breakpoint 8 address */
#define LOONGARCH_CSR_IB8MASK 0x3d1 /* inst breakpoint 8 mask */
#define LOONGARCH_CSR_IB8CTRL 0x3d2 /* inst breakpoint 8 control */
#define LOONGARCH_CSR_IB8ASID 0x3d3 /* inst breakpoint 8 asid */

#define LOONGARCH_CSR_IB9ADDR 0x3d8 /* inst breakpoint 9 address */
#define LOONGARCH_CSR_IB9MASK 0x3d9 /* inst breakpoint 9 mask */
#define LOONGARCH_CSR_IB9CTRL 0x3da /* inst breakpoint 9 control */
#define LOONGARCH_CSR_IB9ASID 0x3db /* inst breakpoint 9 asid */

#define LOONGARCH_CSR_IB10ADDR 0x3e0 /* inst breakpoint 10 address */
#define LOONGARCH_CSR_IB10MASK 0x3e1 /* inst breakpoint 10 mask */
#define LOONGARCH_CSR_IB10CTRL 0x3e2 /* inst breakpoint 10 control */
#define LOONGARCH_CSR_IB10ASID 0x3e3 /* inst breakpoint 10 asid */

#define LOONGARCH_CSR_IB11ADDR 0x3e8 /* inst breakpoint 11 address */
#define LOONGARCH_CSR_IB11MASK 0x3e9 /* inst breakpoint 11 mask */
#define LOONGARCH_CSR_IB11CTRL 0x3ea /* inst breakpoint 11 control */
#define LOONGARCH_CSR_IB11ASID 0x3eb /* inst breakpoint 11 asid */

#define LOONGARCH_CSR_IB12ADDR 0x3f0 /* inst breakpoint 12 address */
#define LOONGARCH_CSR_IB12MASK 0x3f1 /* inst breakpoint 12 mask */
#define LOONGARCH_CSR_IB12CTRL 0x3f2 /* inst breakpoint 12 control */
#define LOONGARCH_CSR_IB12ASID 0x3f3 /* inst breakpoint 12 asid */

#define LOONGARCH_CSR_IB13ADDR 0x3f8 /* inst breakpoint 13 address */
#define LOONGARCH_CSR_IB13MASK 0x3f9 /* inst breakpoint 13 mask */
#define LOONGARCH_CSR_IB13CTRL 0x3fa /* inst breakpoint 13 control */
#define LOONGARCH_CSR_IB13ASID 0x3fb /* inst breakpoint 13 asid */

#define LOONGARCH_CSR_DEBUG 0x500 /* debug config */
#define LOONGARCH_CSR_DERA 0x501 /* debug era */
#define LOONGARCH_CSR_DESAVE 0x502 /* debug save */
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16 changes: 14 additions & 2 deletions arch/loongarch/kernel/hw_breakpoint.c
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Original file line number Diff line number Diff line change
Expand Up @@ -51,7 +51,13 @@ int hw_breakpoint_slots(int type)
READ_WB_REG_CASE(OFF, 4, REG, T, VAL); \
READ_WB_REG_CASE(OFF, 5, REG, T, VAL); \
READ_WB_REG_CASE(OFF, 6, REG, T, VAL); \
READ_WB_REG_CASE(OFF, 7, REG, T, VAL);
READ_WB_REG_CASE(OFF, 7, REG, T, VAL); \
READ_WB_REG_CASE(OFF, 8, REG, T, VAL); \
READ_WB_REG_CASE(OFF, 9, REG, T, VAL); \
READ_WB_REG_CASE(OFF, 10, REG, T, VAL); \
READ_WB_REG_CASE(OFF, 11, REG, T, VAL); \
READ_WB_REG_CASE(OFF, 12, REG, T, VAL); \
READ_WB_REG_CASE(OFF, 13, REG, T, VAL);

#define GEN_WRITE_WB_REG_CASES(OFF, REG, T, VAL) \
WRITE_WB_REG_CASE(OFF, 0, REG, T, VAL); \
Expand All @@ -61,7 +67,13 @@ int hw_breakpoint_slots(int type)
WRITE_WB_REG_CASE(OFF, 4, REG, T, VAL); \
WRITE_WB_REG_CASE(OFF, 5, REG, T, VAL); \
WRITE_WB_REG_CASE(OFF, 6, REG, T, VAL); \
WRITE_WB_REG_CASE(OFF, 7, REG, T, VAL);
WRITE_WB_REG_CASE(OFF, 7, REG, T, VAL); \
WRITE_WB_REG_CASE(OFF, 8, REG, T, VAL); \
WRITE_WB_REG_CASE(OFF, 9, REG, T, VAL); \
WRITE_WB_REG_CASE(OFF, 10, REG, T, VAL); \
WRITE_WB_REG_CASE(OFF, 11, REG, T, VAL); \
WRITE_WB_REG_CASE(OFF, 12, REG, T, VAL); \
WRITE_WB_REG_CASE(OFF, 13, REG, T, VAL);

static u64 read_wb_reg(int reg, int n, int t)
{
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2 changes: 1 addition & 1 deletion arch/loongarch/power/platform.c
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Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@ void enable_gpe_wakeup(void)
if (acpi_gbl_reduced_hardware)
return;

acpi_enable_all_wakeup_gpes();
acpi_hw_enable_all_wakeup_gpes();
}

void enable_pci_wakeup(void)
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2 changes: 0 additions & 2 deletions drivers/acpi/acpica/achware.h
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Expand Up @@ -103,8 +103,6 @@ acpi_hw_get_gpe_status(struct acpi_gpe_event_info *gpe_event_info,

acpi_status acpi_hw_enable_all_runtime_gpes(void);

acpi_status acpi_hw_enable_all_wakeup_gpes(void);

u8 acpi_hw_check_all_gpes(acpi_handle gpe_skip_device, u32 gpe_skip_number);

acpi_status
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1 change: 1 addition & 0 deletions include/acpi/acpixf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -763,6 +763,7 @@ ACPI_HW_DEPENDENT_RETURN_STATUS(acpi_status
*event_status))
ACPI_HW_DEPENDENT_RETURN_UINT32(u32 acpi_dispatch_gpe(acpi_handle gpe_device, u32 gpe_number))
ACPI_HW_DEPENDENT_RETURN_STATUS(acpi_status acpi_hw_disable_all_gpes(void))
ACPI_HW_DEPENDENT_RETURN_STATUS(acpi_status acpi_hw_enable_all_wakeup_gpes(void))
ACPI_HW_DEPENDENT_RETURN_STATUS(acpi_status acpi_disable_all_gpes(void))
ACPI_HW_DEPENDENT_RETURN_STATUS(acpi_status acpi_enable_all_runtime_gpes(void))
ACPI_HW_DEPENDENT_RETURN_STATUS(acpi_status acpi_enable_all_wakeup_gpes(void))
Expand Down
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