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Fix the remaining jitstress-isas-x86 failures #37459

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Merged
tannergooding merged 2 commits into from
Jun 9, 2020
Merged

Fix the remaining jitstress-isas-x86 failures #37459

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d7042a6
Ensure the right SIMD size is used for the AsVector256 AVX code
tannergooding Jun 4, 2020
dccf38d
Don't create GT_SIMD nodes if the baseline ISAs are not supported.
tannergooding Jun 8, 2020
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2 changes: 1 addition & 1 deletion src/coreclr/src/jit/hwintrinsicxarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -707,7 +707,7 @@ GenTree* Compiler::impBaseIntrinsic(NamedIntrinsic intrinsic,
else
{
assert(intrinsic == NI_Vector256_AsVector256);
return impBaseIntrinsic(NI_Vector128_ToVector256, clsHnd, method, sig, baseType, retType, simdSize);
return impBaseIntrinsic(NI_Vector128_ToVector256, clsHnd, method, sig, baseType, retType, 16);
}
}

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19 changes: 19 additions & 0 deletions src/coreclr/src/jit/simd.cpp
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Expand Up @@ -1824,6 +1824,25 @@ GenTree* Compiler::impSIMDIntrinsic(OPCODE opcode,
return nullptr;
}

#if defined(TARGET_XARCH)
CORINFO_InstructionSet minimumIsa = InstructionSet_SSE2;
#elif defined(TARGET_ARM64)
CORINFO_InstructionSet minimumIsa = InstructionSet_AdvSimd;
#else
#error Unsupported platform
#endif // !TARGET_XARCH && !TARGET_ARM64

if (!compOpportunisticallyDependsOn(minimumIsa))
{
// The user disabled support for the baseline ISA so
// don't emit any SIMD intrinsics as they all require
// this at a minimum. We will, however, return false
// for IsHardwareAccelerated as that will help with
// dead code elimination.

return (intrinsicInfo->id == SIMDIntrinsicHWAccel) ? gtNewIconNode(0, TYP_INT) : nullptr;
}

SIMDIntrinsicID simdIntrinsicID = intrinsicInfo->id;
var_types simdType;
if (baseType != TYP_UNKNOWN)
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