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IPC4: TGL: Add multicore support #3711

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IPC4: TGL: Add multicore support #3711

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7d3a0a1
ASoC: SOF: ipc4-pcm: set pcm rate to dai setting
RanderWang Jun 13, 2022
9c7208b
ASoC: SOF: add ipc4 src module support
RanderWang Jun 13, 2022
7a67cb8
ASoC: SOF: ipc4-topology: set domain bit based on dp domain type
RanderWang Jun 13, 2022
c2608f9
ASoC: SOF: IPC4-tooplogy: Add core tokens
ranj063 Mar 9, 2022
d94e66b
ASoC: SOF: tgl: add ipc4 multicore support
fredoh9 Mar 1, 2022
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15 changes: 15 additions & 0 deletions include/sound/sof/ext_manifest4.h
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Original file line number Diff line number Diff line change
Expand Up @@ -90,6 +90,21 @@ struct sof_man4_segment_desc {
uint32_t file_offset;
} __packed;

/*
* bit definition for type in sof_man4_module
* uint32_t load_type : 4; MT_BUILTIN, MT_LOADABLE
* uint32_t auto_start : 1; 0 - manually created, 1 - single instance created by Module Manager
* uint32_t domain_ll : 1; support LL domain
* uint32_t domain_dp : 1; support DP domain
* uint32_t lib_code : 1; determines if module is place holder for common library code
* uint32_t _rsvd : 24;
*/
#define SOF_IPC4_MODULE_LOAD_TYPE(x) ((x) & 0xf)
#define SOF_IPC4_MODULE_AUTO_START(x) (((x) >> 4) & 0x1)
#define SOF_IPC4_MODULE_DOMAIN_LL(x) (((x) >> 5) & 0x1)
#define SOF_IPC4_MODULE_DOMAIN_DP(x) (((x) >> 6) & 0x1)
#define SOF_IPC4_MODULE_LIB_CODE(x) (((x) >> 7) & 0x1)

struct sof_man4_module {
uint32_t id;
uint8_t name[MAX_MODULE_NAME_LEN];
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47 changes: 43 additions & 4 deletions sound/soc/sof/intel/tgl.c
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Expand Up @@ -9,6 +9,7 @@
* Hardware interface for audio DSP on Tigerlake.
*/

#include <sound/sof/ipc4/header.h>
#include <sound/sof/ext_manifest4.h>
#include "../ipc4-priv.h"
#include "../ops.h"
Expand Down Expand Up @@ -50,6 +51,40 @@ static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core)
return 0;
}

static int tgl_dsp_ipc4_core_get(struct snd_sof_dev *sdev, int core)
{
struct sof_ipc4_msg msg;
struct sof_ipc4_dx_info dx_info;

dx_info.core_mask = BIT(core);
dx_info.dx_mask = BIT(core);
msg.primary = SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_MOD_SET_DX);
msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
msg.primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG);
msg.data_ptr = &dx_info;
msg.data_size = sizeof(dx_info);

/* now send the iPC */
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@plbossart plbossart Jun 22, 2022

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IPC

return sof_ipc_tx_message(sdev->ipc, &msg, sizeof(dx_info), NULL, 0);
}

static int tgl_dsp_ipc4_core_put(struct snd_sof_dev *sdev, int core)
{
struct sof_ipc4_msg msg;
struct sof_ipc4_dx_info dx_info;

dx_info.core_mask = BIT(core);
dx_info.dx_mask = ~BIT(core);
msg.primary = SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_MOD_SET_DX);
msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
msg.primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG);
msg.data_ptr = &dx_info;
msg.data_size = sizeof(dx_info);

/* now send the iPC */
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@plbossart plbossart Jun 22, 2022

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IPC

return sof_ipc_tx_message(sdev->ipc, &msg, sizeof(dx_info), NULL, 0);
}

/* Tigerlake ops */
struct snd_sof_dsp_ops sof_tgl_ops;
EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
Expand All @@ -68,6 +103,10 @@ int sof_tgl_ops_init(struct snd_sof_dev *sdev)

/* ipc */
sof_tgl_ops.send_msg = cnl_ipc_send_msg;

/* dsp core get/put */
sof_tgl_ops.core_get = tgl_dsp_core_get;
sof_tgl_ops.core_put = tgl_dsp_core_put;
}

if (sdev->pdata->ipc_type == SOF_INTEL_IPC4) {
Expand All @@ -85,6 +124,10 @@ int sof_tgl_ops_init(struct snd_sof_dev *sdev)

/* ipc */
sof_tgl_ops.send_msg = cnl_ipc4_send_msg;

/* dsp core get/put */
sof_tgl_ops.core_get = tgl_dsp_ipc4_core_get;
sof_tgl_ops.core_put = tgl_dsp_ipc4_core_put;
}

/* set DAI driver ops */
Expand All @@ -101,10 +144,6 @@ int sof_tgl_ops_init(struct snd_sof_dev *sdev)
/* firmware run */
sof_tgl_ops.run = hda_dsp_cl_boot_firmware_iccmax;

/* dsp core get/put */
sof_tgl_ops.core_get = tgl_dsp_core_get;
sof_tgl_ops.core_put = tgl_dsp_core_put;

return 0;
};
EXPORT_SYMBOL_NS(sof_tgl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
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4 changes: 4 additions & 0 deletions sound/soc/sof/ipc4-pcm.c
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Expand Up @@ -179,6 +179,7 @@ static int sof_ipc4_pcm_dai_link_fixup(struct snd_soc_pcm_runtime *rtd,
{
struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, SOF_AUDIO_PCM_DRV_NAME);
struct snd_sof_dai *dai = snd_sof_find_dai(component, rtd->dai_link->name);
struct snd_interval *rate = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
struct sof_ipc4_copier *ipc4_copier;
Expand All @@ -201,6 +202,9 @@ static int sof_ipc4_pcm_dai_link_fixup(struct snd_soc_pcm_runtime *rtd,
snd_mask_none(fmt);
snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S32_LE);

rate->min = ipc4_copier->available_fmt.base_config->audio_fmt.sampling_frequency;
rate->max = rate->min;

/*
* Set trigger order for capture to SND_SOC_DPCM_TRIGGER_PRE. This is required
* to ensure that the BE DAI pipeline gets stopped/suspended before the FE DAI
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10 changes: 10 additions & 0 deletions sound/soc/sof/ipc4-priv.h
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Expand Up @@ -48,4 +48,14 @@ extern const struct sof_ipc_pcm_ops ipc4_pcm_ops;

int sof_ipc4_set_pipeline_state(struct snd_sof_dev *sdev, u32 id, u32 state);

/**
* struct sof_ipc4_dx_info: ipc4 core/Dx mask data
* @core_mask: core mask
* @dx_mask: Dx mask
*/
struct sof_ipc4_dx_info {
u32 core_mask;
u32 dx_mask;
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@plbossart plbossart Jun 22, 2022

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this is very confusing, please describe more.

is core_mask the active cores, the managed cores? Why do we need a new definition?

Likewise Dx means 1 for D0 and 0 for D3? What about D0ix for core0?

};

#endif
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