IPC4: TGL: Add multicore support #3711
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Dsp converts pcm rate to the one defined by dai. When SRC is used, the pcm runtime rate is different with dai rate and we need to fix it up for BE components. Signed-off-by: Rander Wang <rander.wang@intel.com>
Src module only needs two parameters : base module config and sink rate. This PR add prepare and setup for src widgets. Signed-off-by: Rander Wang <rander.wang@intel.com>
Currently the domain bit in ipc msg for module initialization is set to lp mode for pipeline. This is not correct since it is for module domain type: ll domain or dp domain which are for scheduler in fw. The domain bit depends on dp domain setting. Signed-off-by: Rander Wang <rander.wang@intel.com>
Add support for parsing core token. Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Add core_get/core_put to support core power up/down for IPC4. Signed-off-by: Fred Oh <fred.oh@linux.intel.com>
plbossart
requested changes
Jun 22, 2022
| msg.data_ptr = &dx_info; | ||
| msg.data_size = sizeof(dx_info); | ||
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| /* now send the iPC */ |
| msg.data_ptr = &dx_info; | ||
| msg.data_size = sizeof(dx_info); | ||
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| /* now send the iPC */ |
sound/soc/sof/ipc4-topology.h
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| struct sof_ipc4_available_audio_format available_fmt; | ||
| struct sof_ipc4_msg msg; | ||
| }; | ||
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| */ | ||
| struct sof_ipc4_dx_info { | ||
| u32 core_mask; | ||
| u32 dx_mask; |
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this is very confusing, please describe more.
is core_mask the active cores, the managed cores? Why do we need a new definition?
Likewise Dx means 1 for D0 and 0 for D3? What about D0ix for core0?
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Will merge this to #3679 |
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Currently this is based on Rander's SRC PR, #3692. Last two are additional changes for IPC4 TGL multicore support.
The topology I tested is also based on Rander's PR, thesofproject/sof#5913. And I set core_id 1 on SRC module. Topology graph is like this.