soundwire: intel: simplify sync_go sequence #4153
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In the existing code, the SHIM_SYNC::SYNC_GO bit is set, and the code waits for it to return to zero. That second wait part is just wrong: the SYNC_GO bit is *write-only* so there's no way to know if it's cleared by hardware. The code works because the value for a read-only bit is zero, but that's really just luck. Simplify the sequence to a plain read-modify-write. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
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ujfalusi
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now it makes more sense.
ranj063
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plbossart
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additional simplifications are possible, closing for now. |
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actually no, it's too complicated to simplify further. |
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@plbossart the CML SDW tests are failing with this PR. Is this a known issue or is this because of this PR |
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Ok looks like its happening in other PRs too |
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yes, that board has severe issues with timeouts in suspend/resume. I don't think it's related to this PR. |
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bardliao
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already merged with #4157 |
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In the existing code, the SHIM_SYNC::SYNC_GO bit is set, and the code waits for it to return to zero.
That second wait part is just wrong: the SYNC_GO bit is write-only so there's no way to know if it's cleared by hardware. The code works because the value for a read-only bit is zero, but that's really just luck.
Simplify the sequence to a plain read-modify-write.
Signed-off-by: Pierre-Louis Bossart pierre-louis.bossart@linux.intel.com