[BUG] Shared per core arrays need elems aligned to cache size on Intel DSPs #5589
Description
Describe the bug
Arrays of structures can only be aligned in memory for the address of elem[0] but not thereafter. elems[1+] is not guaranteed to be aligned with any compiler attribute. This causes an issue even when the array in in uncache region if any client converts the elem to cached reference (which appears to be happening). See #5512
We have the following candidates (I have reduced the list below in the comments to only include the users from a Zephyr perspective).
grep -rn "\[CONFIG_CORE_COUNT" --include=*.c --include=*.h zephyr/* src/*
zephyr/schedule.c:15:static struct schedulers *_schedulers[CONFIG_CORE_COUNT];
zephyr/wrapper.c:460:static struct notify *host_notify[CONFIG_CORE_COUNT];
src/arch/xtensa/xtos/int-sethandler.c:34:extern struct xtos_core_data *core_data_ptr[CONFIG_CORE_COUNT];
src/arch/xtensa/init.c:49:struct core_context *core_ctx_ptr[CONFIG_CORE_COUNT] = { 0 };
src/arch/xtensa/init.c:55:struct xtos_core_data *core_data_ptr[CONFIG_CORE_COUNT] = { 0 };
src/arch/xtensa/lib/cpu.c:32:extern struct core_context *core_ctx_ptr[CONFIG_CORE_COUNT];
src/arch/xtensa/lib/cpu.c:33:extern struct xtos_core_data *core_data_ptr[CONFIG_CORE_COUNT];
src/idc/idc.c:36:static SHARED_DATA struct idc_payload static_payload[CONFIG_CORE_COUNT];
src/include/sof/drivers/interrupt.h:28: int enable_count[CONFIG_CORE_COUNT]; /**< IRQ enable counter */
src/include/sof/drivers/interrupt.h:88: int enable_count[CONFIG_CORE_COUNT]; /**< enabled child
src/include/sof/drivers/interrupt.h:91: unsigned int num_children[CONFIG_CORE_COUNT]; /**< number of children
src/include/sof/schedule/ll_schedule_domain.h:58: bool enabled[CONFIG_CORE_COUNT]; /**< enabled cores */
src/ipc/ipc3/dai.c:179: bool comp_on_core[CONFIG_CORE_COUNT] = { false };
src/lib/notifier.c:28:static SHARED_DATA struct notify_data notify_data[CONFIG_CORE_COUNT];
src/lib/dai.c:30:static struct dai_group_list *groups[CONFIG_CORE_COUNT];
src/platform/intel/cavs/include/cavs/lib/pm_runtime.h:39: int dsp_client_bitmap[CONFIG_CORE_COUNT]; /**< simple pwr override */
src/platform/intel/cavs/platform.c:277:static SHARED_DATA struct timer arch_timers[CONFIG_CORE_COUNT];
src/platform/intel/cavs/lib/clk.c:82: k_spinlock_key_t key[CONFIG_CORE_COUNT];
src/platform/intel/cavs/lib/memory.c:35: sys_rt_x_block64[CONFIG_CORE_COUNT - 1][HEAP_SYS_RT_X_COUNT64];
src/platform/intel/cavs/lib/memory.c:37: sys_rt_x_block512[CONFIG_CORE_COUNT - 1][HEAP_SYS_RT_X_COUNT512];
src/platform/intel/cavs/lib/memory.c:39: sys_rt_x_block1024[CONFIG_CORE_COUNT - 1][HEAP_SYS_RT_X_COUNT1024];
src/platform/intel/cavs/lib/memory.c:43:static SHARED_DATA struct block_map sys_rt_heap_map[CONFIG_CORE_COUNT][3] = {
src/platform/library/lib/memory.c:37: sys_rt_x_block64[CONFIG_CORE_COUNT - 1][HEAP_SYS_RT_X_COUNT64];
src/platform/library/lib/memory.c:39: sys_rt_x_block512[CONFIG_CORE_COUNT - 1][HEAP_SYS_RT_X_COUNT512];
src/platform/library/lib/memory.c:41: sys_rt_x_block1024[CONFIG_CORE_COUNT - 1][HEAP_SYS_RT_X_COUNT1024];
src/platform/library/lib/memory.c:45:static SHARED_DATA struct block_map sys_rt_heap_map[CONFIG_CORE_COUNT][3] = {
src/schedule/timer_domain.c:27: void *arg[CONFIG_CORE_COUNT];
src/schedule/zephyr_domain.c:51: struct zephyr_domain_thread domain_thread[CONFIG_CORE_COUNT];
src/schedule/dma_single_chan_domain.c:44: struct dma_domain_data data[CONFIG_CORE_COUNT];
src/schedule/dma_multi_chan_domain.c:54: uint32_t channel_mask[PLATFORM_NUM_DMACS][CONFIG_CORE_COUNT];
src/schedule/dma_multi_chan_domain.c:56: struct dma_domain_data *arg[PLATFORM_NUM_DMACS][CONFIG_CORE_COUNT];
src/schedule/zephyr.c:95:static struct zephyr_idc_msg idc_work[CONFIG_CORE_COUNT];
src/trace/trace.c:55: struct recent_trace_context trace_core_context[CONFIG_CORE_COUNT];
Expected behavior
All shared arrays should have elements cached aligned.
Impact
High and unpredictable impact. Easy to regress.