A library for inspecting combinational digital circuits from Verilog netlists, focusing on exploring energy limits based on Landauer's principle.

Design and implementation of an ASIC with an 8051 microcontroller core. Includes VHDL modules, C applications, RTL simulations, and mixed-signal validation. Focused on hardware-software co-design and optimization.

The project uses an ML surrogate model (e.g., Random Forest) to instantly predict a decoder's PPA (Power, Performance, Area) based on design parameters optimizing trade-off, significantly boosting efficiency and enabling a faster, data-driven VLSI design flow .