systolic-arrays

Here are 12 public repositories matching this topic...

rejunity / tiny-asic-1_58bit-matrix-mul

Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit

asic systolic-arrays tinytapeout llm-inference

Updated Apr 19, 2024
Verilog

jiaaom / HPDLA

Star

Systolic-array based Deep Learning Accelerator generator

chisel3 dla systolic-arrays

Updated Dec 11, 2020
Verilog

jasonlin316 / Systolic-Array-for-Smith-Waterman

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This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times faster than a software running the same algorithm.

local smith-waterman verilog dynamic-programming sequence-alignment short-read systolic-arrays

Updated Jul 4, 2019
Verilog

AIC2021 / AIC2021_TPU_Template

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Template for project1 TPU

accelerator matrix-multiplication tpu systolic-arrays

Updated May 1, 2021
Verilog

akira2963753 / Low-Cost-AI-Accelerator-Based-on-TPU

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This is my senior project, we aim to design a Low-cost-AI-Accelerator based on Google's Tensor Processing Unit.

asic ics ic-design tpu systolic-arrays low-cost-ai asic-design ai-accelerators ai-accelerator

Updated Nov 16, 2025
Verilog

minhsun-c / FP32-Matrix-Multiplier

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High-performance systolic-array accelerator for FP32 matrix multiplication in deep learning.

pipeline verilog ieee754 verilator systolic-arrays

Updated Oct 5, 2025
Verilog

Noamv7 / Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification

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This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.

verification matrix-multiplication verilog systemverilog questasim logic-design sva systolic-arrays amba-apb functional-coverage chip-design

Updated Jun 26, 2024
Verilog

KevinWang96 / EE599_YihaoWang_7410178057

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EE599 Accelerated Computing on FPGA

fpga matrix-multiplication verilog vivado odd-even-sort barrel-shifter systolic-arrays

Updated Apr 3, 2020
Verilog

InnisChen / STRAIT-Self-Test-and-Self-Recovery-for-AI-Accelerator

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This is my senior project. Aims to implement the AI accelerator self-test and self-recovery architecture proposed in the paper "STRAIT: Self-Test and Self-Recovery for AI Accelerator". STRAIT is a unified solution that provides self-test, self-diagnosis, and self-recovery functions for systolic array-based AI accelerators.

diagnostics ics tpu bist systolic-arrays ai-accelerators bisr vlsi-testing