feat(prover): add MEMW_A aligned-memory fast path table

[nicole-graus]

Description

Implements the MEMW_A aligned fast path from spec PR #398.

Adds a new 30-column table for memory/register accesses where all bytes share the same
old_timestamp (aligned ops). Operations are routed at trace build time: aligned ops with uniform
timestamps go to MEMW_A, the rest go to MEMW.

• 30 columns, 20 bus interactions, 2 algebraic constraints.
• Address decomposed into high/mid/low parts; AND_BYTE interaction for alignment check.
• Single shared old_timestamp instead of per-byte (8× fewer LT checks).
• All register operations route here by default.

[github-actions]

Codex Code Review

Findings

1. High (Security/Soundness): MEMW_A relies on off-circuit routing for a proof-critical invariant

• The new table explicitly assumes uniform per-byte old_timestamp is “verified by the routing logic,” then stores only old_timestamp[0] and enforces only one LT check.
• References:
  • memw_aligned.rs:84
  • memw_aligned.rs:125
  • memw_aligned.rs:777
  • trace_builder.rs:792
• Why this matters: prover soundness must be enforced by AIR/bus constraints, not by trusted trace-construction logic. A malicious prover is not required to use is_aligned_op.
• Action: enforce the uniform-timestamp invariant in-circuit (or keep such ops in MEMW). Right now the invariant is only a host-side convention.

2. Low (Bug/Robustness): possible panic on unexpected width in is_aligned_op

• for i in 1..op.width as usize { ... op.old_timestamp[i] ... } can index out of bounds if width > 8.
• Reference: trace_builder.rs:802
• Action: guard width explicitly (matches!(width, 1|2|4|8)) before indexing.

Assumptions / gaps

• I could not run tests in this sandbox because Rust toolchain update tries to write under a read-only rustup path.

[claude]

Review: feat(prover) — MEMW_A aligned-memory fast path

Overall the implementation is correct and well-structured. The routing logic, bus interaction format, alignment/timestamp checks, and constraint set all look sound. Two minor issues noted below (see inline comments).

Security / correctness

No vulnerabilities found. Specific points verified:

• CO24/CO25 bus fingerprint format matches the original MEMW table exactly (field ordering: old[8], is_register, addr_lo, addr_hi, value[8], ts, write_flags for reads; is_register, addr_lo, addr_hi, value[8], ts, write_flags for writes).
• The missing R1-R3 address-overflow LT checks in collect_lt_from_memw_aligned are intentionally correct: for a power-of-2 width N, the largest N-aligned u64 is 2^64-N, so addr+(N-1) = 2^64-1 — no wrap is possible. The omission just needs a comment (see inline).
• AND_BYTE alignment mask write2·1 + write4·3 + write8·7 correctly encodes width-1 for each valid width (1→0, 2→1, 4→3, 8→7).
• Padding rows are all-zero; mu_sum=0 suppresses every bus interaction, so no phantom LT/bitwise entries are needed.
• The single shared old_timestamp is gated by is_aligned_op's uniform-timestamp check before routing.

Issues

1. Low (inline on trace_builder.rs:784) — collect_lt_from_memw_aligned silently drops R1-R3 overflow checks with no explanation; add a one-line comment.
2. Low (inline on memw_aligned.rs:20) — PR description says "20 bus interactions" but there are 22; the file header is correct.

[nicole-graus]

/bench

[github-actions]

Benchmark — fib_iterative_8M (median of 3)

_{Table parallelism: 32 (auto = cores / 3)}

Metric	main	PR	Δ
Peak heap	256201 MB	250991 MB	-5210 MB (-2.0%) ⚪
Prove time	105.611s	99.212s	-6.399s (-6.1%) 🟢

🎉 Improvement detected — heap or time decreased by more than 5%.

✅ Low variance (time: 1.6%, heap: 0.3%)

_{Commit: 49bf320 · Baseline: cached · Runner: self-hosted bench}

[diegokingston]

/bench

[nicole-graus]

/bench

[diegokingston]

/bench

[diegokingston]

/bench

[nicole-graus]

/bench

[nicole-graus]

/bench

[nicole-graus]

/bench

[nicole-graus]

/bench

[MauroToscano]

We need to understand why there is no improvement