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Move GetLclOffs method to GenTreeLclVarCommon. #39623

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Merged
sandreenko merged 3 commits into from
Jul 22, 2020
Merged

Move GetLclOffs method to GenTreeLclVarCommon. #39623

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b67a916
Move `GetLclOffs` to `Common`.
Jul 20, 2020
503a792
Start using it.
Jul 20, 2020
bb173eb
Review response.
Jul 22, 2020
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19 changes: 8 additions & 11 deletions src/coreclr/src/jit/codegenarm64.cpp
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Expand Up @@ -4699,7 +4699,7 @@ void CodeGen::genStoreIndTypeSIMD12(GenTree* treeNode)

genConsumeOperands(treeNode->AsOp());

// Need an addtional integer register to extract upper 4 bytes from data.
// Need an additional integer register to extract upper 4 bytes from data.
regNumber tmpReg = treeNode->GetSingleTempReg();
assert(tmpReg != addr->GetRegNum());

Expand Down Expand Up @@ -4766,16 +4766,13 @@ void CodeGen::genStoreLclTypeSIMD12(GenTree* treeNode)
{
assert((treeNode->OperGet() == GT_STORE_LCL_FLD) || (treeNode->OperGet() == GT_STORE_LCL_VAR));

unsigned offs = 0;
unsigned varNum = treeNode->AsLclVarCommon()->GetLclNum();
assert(varNum < compiler->lvaCount);
GenTreeLclVarCommon* lclVar = treeNode->AsLclVarCommon();

if (treeNode->OperGet() == GT_STORE_LCL_FLD)
{
offs = treeNode->AsLclFld()->GetLclOffs();
}
unsigned offs = lclVar->GetLclOffs();
unsigned varNum = lclVar->GetLclNum();
assert(varNum < compiler->lvaCount);

GenTree* op1 = treeNode->AsOp()->gtOp1;
GenTree* op1 = lclVar->gtGetOp1();

if (op1->isContained())
{
Expand All @@ -4792,8 +4789,8 @@ void CodeGen::genStoreLclTypeSIMD12(GenTree* treeNode)
}
regNumber operandReg = genConsumeReg(op1);

// Need an addtional integer register to extract upper 4 bytes from data.
regNumber tmpReg = treeNode->GetSingleTempReg();
// Need an additional integer register to extract upper 4 bytes from data.
regNumber tmpReg = lclVar->GetSingleTempReg();
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@AndyAyersMS AndyAyersMS Jul 22, 2020

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Can you fix the typo in the line above? addtional -> additional

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@sandreenko sandreenko Jul 22, 2020

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Done.


// store lower 8 bytes
GetEmitter()->emitIns_S_R(INS_str, EA_8BYTE, operandReg, varNum, offs);
Expand Down
24 changes: 4 additions & 20 deletions src/coreclr/src/jit/codegenarmarch.cpp
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Expand Up @@ -1959,11 +1959,7 @@ void CodeGen::genCodeForInitBlkUnroll(GenTreeBlk* node)
{
assert(dstAddr->OperIsLocalAddr());
dstLclNum = dstAddr->AsLclVarCommon()->GetLclNum();

if (dstAddr->OperIs(GT_LCL_FLD_ADDR))
{
dstOffset = dstAddr->AsLclFld()->GetLclOffs();
}
dstOffset = dstAddr->AsLclVarCommon()->GetLclOffs();
}

regNumber srcReg;
Expand Down Expand Up @@ -2095,11 +2091,7 @@ void CodeGen::genCodeForCpBlkUnroll(GenTreeBlk* node)

assert(dstAddr->OperIsLocalAddr());
dstLclNum = dstAddr->AsLclVarCommon()->GetLclNum();

if (dstAddr->OperIs(GT_LCL_FLD_ADDR))
{
dstOffset = dstAddr->AsLclFld()->GetLclOffs();
}
dstOffset = dstAddr->AsLclVarCommon()->GetLclOffs();
}

unsigned srcLclNum = BAD_VAR_NUM;
Expand All @@ -2112,11 +2104,7 @@ void CodeGen::genCodeForCpBlkUnroll(GenTreeBlk* node)
if (src->OperIs(GT_LCL_VAR, GT_LCL_FLD))
{
srcLclNum = src->AsLclVarCommon()->GetLclNum();

if (src->OperIs(GT_LCL_FLD))
{
srcOffset = src->AsLclFld()->GetLclOffs();
}
srcOffset = src->AsLclVarCommon()->GetLclOffs();
}
else
{
Expand All @@ -2136,11 +2124,7 @@ void CodeGen::genCodeForCpBlkUnroll(GenTreeBlk* node)
{
assert(srcAddr->OperIsLocalAddr());
srcLclNum = srcAddr->AsLclVarCommon()->GetLclNum();

if (srcAddr->OperIs(GT_LCL_FLD_ADDR))
{
srcOffset = srcAddr->AsLclFld()->GetLclOffs();
}
srcOffset = srcAddr->AsLclVarCommon()->GetLclOffs();
}
}

Expand Down
8 changes: 2 additions & 6 deletions src/coreclr/src/jit/codegenlinear.cpp
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Expand Up @@ -1741,15 +1741,11 @@ void CodeGen::genConsumePutStructArgStk(GenTreePutArgStk* putArgNode,
{
// The OperLocalAddr is always contained.
assert(srcAddr->isContained());
GenTreeLclVarCommon* lclNode = srcAddr->AsLclVarCommon();
const GenTreeLclVarCommon* lclNode = srcAddr->AsLclVarCommon();

// Generate LEA instruction to load the LclVar address in RSI.
// Source is known to be on the stack. Use EA_PTRSIZE.
unsigned int offset = 0;
if (srcAddr->OperGet() == GT_LCL_FLD_ADDR)
{
offset = srcAddr->AsLclFld()->GetLclOffs();
}
unsigned int offset = lclNode->GetLclOffs();
GetEmitter()->emitIns_R_S(INS_lea, EA_PTRSIZE, srcReg, lclNode->GetLclNum(), offset);
}
else
Expand Down
42 changes: 11 additions & 31 deletions src/coreclr/src/jit/codegenxarch.cpp
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Expand Up @@ -2694,11 +2694,7 @@ void CodeGen::genCodeForInitBlkUnroll(GenTreeBlk* node)
{
assert(dstAddr->OperIsLocalAddr());
dstLclNum = dstAddr->AsLclVarCommon()->GetLclNum();

if (dstAddr->OperIs(GT_LCL_FLD_ADDR))
{
dstOffset = dstAddr->AsLclFld()->GetLclOffs();
}
dstOffset = dstAddr->AsLclVarCommon()->GetLclOffs();
}

regNumber srcIntReg = REG_NA;
Expand Down Expand Up @@ -2819,11 +2815,9 @@ void CodeGen::genCodeForLoadOffset(instruction ins, emitAttr size, regNumber dst

if (baseNode->OperIsLocalAddr())
{
if (baseNode->gtOper == GT_LCL_FLD_ADDR)
{
offset += baseNode->AsLclFld()->GetLclOffs();
}
emit->emitIns_R_S(ins, size, dst, baseNode->AsLclVarCommon()->GetLclNum(), offset);
const GenTreeLclVarCommon* lclVar = baseNode->AsLclVarCommon();
offset += lclVar->GetLclOffs();
emit->emitIns_R_S(ins, size, dst, lclVar->GetLclNum(), offset);
}
else
{
Expand Down Expand Up @@ -2873,12 +2867,9 @@ void CodeGen::genCodeForCpBlkUnroll(GenTreeBlk* node)
else
{
assert(dstAddr->OperIsLocalAddr());
dstLclNum = dstAddr->AsLclVarCommon()->GetLclNum();

if (dstAddr->OperIs(GT_LCL_FLD_ADDR))
{
dstOffset = dstAddr->AsLclFld()->GetLclOffs();
}
const GenTreeLclVarCommon* lclVar = dstAddr->AsLclVarCommon();
dstLclNum = lclVar->GetLclNum();
dstOffset = lclVar->GetLclOffs();
}

unsigned srcLclNum = BAD_VAR_NUM;
Expand All @@ -2893,11 +2884,7 @@ void CodeGen::genCodeForCpBlkUnroll(GenTreeBlk* node)
if (src->OperIs(GT_LCL_VAR, GT_LCL_FLD))
{
srcLclNum = src->AsLclVarCommon()->GetLclNum();

if (src->OperIs(GT_LCL_FLD))
{
srcOffset = src->AsLclFld()->GetLclOffs();
}
srcOffset = src->AsLclVarCommon()->GetLclOffs();
}
else
{
Expand Down Expand Up @@ -2929,11 +2916,7 @@ void CodeGen::genCodeForCpBlkUnroll(GenTreeBlk* node)
{
assert(srcAddr->OperIsLocalAddr());
srcLclNum = srcAddr->AsLclVarCommon()->GetLclNum();

if (srcAddr->OperIs(GT_LCL_FLD_ADDR))
{
srcOffset = srcAddr->AsLclFld()->GetLclOffs();
}
srcOffset = srcAddr->AsLclVarCommon()->GetLclOffs();
}
}

Expand Down Expand Up @@ -7941,11 +7924,8 @@ void CodeGen::genPutStructArgStk(GenTreePutArgStk* putArgStk)
{
assert(srcAddr->OperIsLocalAddr());

srcLclNum = srcAddr->AsLclVarCommon()->GetLclNum();
if (srcAddr->OperGet() == GT_LCL_FLD_ADDR)
{
srcLclOffset = srcAddr->AsLclFld()->GetLclOffs();
}
srcLclNum = srcAddr->AsLclVarCommon()->GetLclNum();
srcLclOffset = srcAddr->AsLclVarCommon()->GetLclOffs();
}

for (int i = numSlots - 1; i >= 0; --i)
Expand Down
6 changes: 1 addition & 5 deletions src/coreclr/src/jit/emitarm64.cpp
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Expand Up @@ -13396,11 +13396,7 @@ void emitter::emitInsLoadStoreOp(instruction ins, emitAttr attr, regNumber dataR
{
GenTreeLclVarCommon* varNode = addr->AsLclVarCommon();
unsigned lclNum = varNode->GetLclNum();
unsigned offset = 0;
if (addr->OperIs(GT_LCL_FLD_ADDR))
{
offset = varNode->AsLclFld()->GetLclOffs();
}
unsigned offset = varNode->GetLclOffs();
if (emitInsIsStore(ins))
{
emitIns_S_R(ins, attr, dataReg, lclNum, offset);
Expand Down
6 changes: 1 addition & 5 deletions src/coreclr/src/jit/emitxarch.cpp
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Expand Up @@ -3100,11 +3100,7 @@ void emitter::emitInsStoreInd(instruction ins, emitAttr attr, GenTreeStoreInd* m
if (addr->OperIs(GT_LCL_VAR_ADDR, GT_LCL_FLD_ADDR))
{
GenTreeLclVarCommon* varNode = addr->AsLclVarCommon();
unsigned offset = 0;
if (addr->OperIs(GT_LCL_FLD_ADDR))
{
offset = varNode->AsLclFld()->GetLclOffs();
}
unsigned offset = varNode->GetLclOffs();
if (data->isContainedIntOrIImmed())
{
emitIns_S_I(ins, attr, varNode->GetLclNum(), offset, (int)data->AsIntConCommon()->IconValue());
Expand Down
25 changes: 20 additions & 5 deletions src/coreclr/src/jit/gentree.cpp
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Expand Up @@ -16365,11 +16365,7 @@ bool GenTree::DefinesLocalAddr(Compiler* comp, unsigned width, GenTreeLclVarComm
*pLclVarTree = addrArgLcl;
if (pIsEntire != nullptr)
{
unsigned lclOffset = 0;
if (addrArg->OperIsLocalField())
{
lclOffset = addrArg->AsLclFld()->GetLclOffs();
}
unsigned lclOffset = addrArgLcl->GetLclOffs();

if (lclOffset != 0)
{
Expand Down Expand Up @@ -19350,6 +19346,25 @@ regNumber GenTree::ExtractTempReg(regMaskTP mask /* = (regMaskTP)-1 */)
return genRegNumFromMask(tempRegMask);
}

//------------------------------------------------------------------------
// GetLclOffs: if `this` is a field or a field address it returns offset
// of the field inside the struct, for not a field it returns 0.
//
// Return Value:
// The offset value.
//
uint16_t GenTreeLclVarCommon::GetLclOffs() const
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@AndyAyersMS AndyAyersMS Jul 22, 2020

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Header comment?

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@sandreenko sandreenko Jul 22, 2020

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Added.

{
if (OperIsLocalField())
{
return AsLclFld()->GetLclOffs();
}
else
{
return 0;
}
}

#ifdef TARGET_ARM
//------------------------------------------------------------------------
// IsOffsetMisaligned: check if the field needs a special handling on arm.
Expand Down
2 changes: 2 additions & 0 deletions src/coreclr/src/jit/gentree.h
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Expand Up @@ -3180,6 +3180,8 @@ struct GenTreeLclVarCommon : public GenTreeUnOp
_gtSsaNum = SsaConfig::RESERVED_SSA_NUM;
}

uint16_t GetLclOffs() const;

unsigned GetSsaNum() const
{
return _gtSsaNum;
Expand Down
2 changes: 1 addition & 1 deletion src/coreclr/src/jit/morph.cpp
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Expand Up @@ -4602,7 +4602,7 @@ GenTree* Compiler::fgMorphMultiregStructArg(GenTree* arg, fgArgTabEntry* fgEntry
assert(varNum < lvaCount);
LclVarDsc* varDsc = &lvaTable[varNum];

unsigned baseOffset = argValue->OperIs(GT_LCL_FLD) ? argValue->AsLclFld()->GetLclOffs() : 0;
unsigned baseOffset = varNode->GetLclOffs();
unsigned lastOffset = baseOffset + structSize;

// The allocated size of our LocalVar must be at least as big as lastOffset
Expand Down
31 changes: 12 additions & 19 deletions src/coreclr/src/jit/simdcodegenxarch.cpp
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Expand Up @@ -585,9 +585,9 @@ void CodeGen::genSIMDIntrinsicInit(GenTreeSIMD* simdNode)
}
else if (op1->OperIsLocalAddr())
{
unsigned offset = op1->OperIs(GT_LCL_FLD_ADDR) ? op1->AsLclFld()->GetLclOffs() : 0;
GetEmitter()->emitIns_R_S(ins, emitTypeSize(targetType), targetReg, op1->AsLclVarCommon()->GetLclNum(),
offset);
const GenTreeLclVarCommon* lclVar = op1->AsLclVarCommon();
unsigned offset = lclVar->GetLclOffs();
GetEmitter()->emitIns_R_S(ins, emitTypeSize(targetType), targetReg, lclVar->GetLclNum(), offset);
}
else
{
Expand Down Expand Up @@ -2143,17 +2143,14 @@ void CodeGen::genStoreLclTypeSIMD12(GenTree* treeNode)
{
assert((treeNode->OperGet() == GT_STORE_LCL_FLD) || (treeNode->OperGet() == GT_STORE_LCL_VAR));

unsigned offs = 0;
unsigned varNum = treeNode->AsLclVarCommon()->GetLclNum();
assert(varNum < compiler->lvaCount);
const GenTreeLclVarCommon* lclVar = treeNode->AsLclVarCommon();

if (treeNode->OperGet() == GT_STORE_LCL_FLD)
{
offs = treeNode->AsLclFld()->GetLclOffs();
}
unsigned offs = lclVar->GetLclOffs();
unsigned varNum = lclVar->GetLclNum();
assert(varNum < compiler->lvaCount);

regNumber tmpReg = treeNode->GetSingleTempReg();
GenTree* op1 = treeNode->AsOp()->gtOp1;
GenTree* op1 = lclVar->gtOp1;
if (op1->isContained())
{
// This is only possible for a zero-init.
Expand Down Expand Up @@ -2197,16 +2194,12 @@ void CodeGen::genLoadLclTypeSIMD12(GenTree* treeNode)
{
assert((treeNode->OperGet() == GT_LCL_FLD) || (treeNode->OperGet() == GT_LCL_VAR));

regNumber targetReg = treeNode->GetRegNum();
unsigned offs = 0;
unsigned varNum = treeNode->AsLclVarCommon()->GetLclNum();
const GenTreeLclVarCommon* lclVar = treeNode->AsLclVarCommon();
regNumber targetReg = lclVar->GetRegNum();
unsigned offs = lclVar->GetLclOffs();
unsigned varNum = lclVar->GetLclNum();
assert(varNum < compiler->lvaCount);

if (treeNode->OperGet() == GT_LCL_FLD)
{
offs = treeNode->AsLclFld()->GetLclOffs();
}

// Need an additional Xmm register that is different from targetReg to read upper 4 bytes.
regNumber tmpReg = treeNode->GetSingleTempReg();
assert(tmpReg != targetReg);
Expand Down