asm: SSE ALU Instructions#10316
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abrown merged 6 commits intobytecodealliance:mainfrom Mar 6, 2025
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implement sse xorpd, addpd, subpd, andpd implement addps, andps, subps
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Had a couple of code movement comments but overall this all makes sense to me. Thanks!
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In [bytecodealliance#10408], the new assembler re-opened an old issue related to unaligned loads with SSE instructions. SSE instructions expect 128-bit aligned loads when using the `m128` operand and fault if that is not the case. This had been fixed previously by disallowing load-sinking for `XmmMem` ([bytecodealliance#4891]) but more recently we had adopted the use of `XmmMemAligned` in `cranelift-codegen`. Since [bytecodealliance#10316] had no knowledge of `XmmMemAligned` (only `XmmMem`), it caused the same kind fault--an OOB trap that was in fact an unaligned load. Why didn't CI catch this? Since all the CI machines have AVX and we do not explicitly test the SSE-only case, these unaligned, sunk loads would use the AVX lowering in CI. AVX loads handle unaligned accesses without a fault. This was only discovered during fuzzing when AVX was disabled (i.e., `--target x86_64-unknown-linux-gnu`). To fix this, this change adopts the `XmmMemAligned` type in the generated assembler code. This is temporary, though: a more lasting fix should pass along an "alignment required" bit from the assembler AST. In the meantime, this closes bytecodealliance#10408. [bytecodealliance#10408]: bytecodealliance#10408 [bytecodealliance#4891]: bytecodealliance#4891 [bytecodealliance#10316]: bytecodealliance#10316
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…10417) In [#10408], the new assembler re-opened an old issue related to unaligned loads with SSE instructions. SSE instructions expect 128-bit aligned loads when using the `m128` operand and fault if that is not the case. This had been fixed previously by disallowing load-sinking for `XmmMem` ([#4891]) but more recently we had adopted the use of `XmmMemAligned` in `cranelift-codegen`. Since [#10316] had no knowledge of `XmmMemAligned` (only `XmmMem`), it caused the same kind fault--an OOB trap that was in fact an unaligned load. Why didn't CI catch this? Since all the CI machines have AVX and we do not explicitly test the SSE-only case, these unaligned, sunk loads would use the AVX lowering in CI. AVX loads handle unaligned accesses without a fault. This was only discovered during fuzzing when AVX was disabled (i.e., `--target x86_64-unknown-linux-gnu`). To fix this, this change adopts the `XmmMemAligned` type in the generated assembler code. This is temporary, though: a more lasting fix should pass along an "alignment required" bit from the assembler AST. In the meantime, this closes #10408. [#10408]: #10408 [#4891]: #4891 [#10316]: #10316
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Implement the following SSE instructions:
xorpdxorpsandpdandpsaddpdaddpssubpdsubpsorpsThe opcode for
*psvariants of these instructions isNP 0F xx. NP has the following explanation in manual:There is an existing
NoPrefixprefix, but I have not reused that to serve aboveNPas there might be some difference in the intended meaning. Also,NPdoesn't classify as a prefix technically. I am thinking to address this in a later patch which would deal with prefix parsing. Any thoughts or feedback on this is welcome.My thinking is
NPdoesn't functionally do anything, so it is fine to ignore it. We just need a way forvalidatefunction to check this.