x64: fix misaligned load fault with sunk load when AVX is disabled#10417
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alexcrichton merged 1 commit intobytecodealliance:mainfrom Mar 18, 2025
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x64: fix misaligned load fault with sunk load when AVX is disabled#10417alexcrichton merged 1 commit intobytecodealliance:mainfrom
alexcrichton merged 1 commit intobytecodealliance:mainfrom
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In [bytecodealliance#10408], the new assembler re-opened an old issue related to unaligned loads with SSE instructions. SSE instructions expect 128-bit aligned loads when using the `m128` operand and fault if that is not the case. This had been fixed previously by disallowing load-sinking for `XmmMem` ([bytecodealliance#4891]) but more recently we had adopted the use of `XmmMemAligned` in `cranelift-codegen`. Since [bytecodealliance#10316] had no knowledge of `XmmMemAligned` (only `XmmMem`), it caused the same kind fault--an OOB trap that was in fact an unaligned load. Why didn't CI catch this? Since all the CI machines have AVX and we do not explicitly test the SSE-only case, these unaligned, sunk loads would use the AVX lowering in CI. AVX loads handle unaligned accesses without a fault. This was only discovered during fuzzing when AVX was disabled (i.e., `--target x86_64-unknown-linux-gnu`). To fix this, this change adopts the `XmmMemAligned` type in the generated assembler code. This is temporary, though: a more lasting fix should pass along an "alignment required" bit from the assembler AST. In the meantime, this closes bytecodealliance#10408. [bytecodealliance#10408]: bytecodealliance#10408 [bytecodealliance#4891]: bytecodealliance#4891 [bytecodealliance#10316]: bytecodealliance#10316
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This change improves the definitions of the assembler's SSE instructions in two ways: - vector instructions that require aligned memory accesses (i.e., most everything pre-AVX) are now noted with an `align` attribute in the AST. This is used for generating the expected `XmmMemAligned` types in `cranelift-codegen-meta` the "right way," resolving the temporary fix introduced in bytecodealliance#10417. - previously-added vector instructions did not have the correct feature flags; this change adds the `sse` feature and also tags the applicable instructions with the `compat` feature to allow their use in some future 32-bit target.
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* asm: notate instruction alignment, SSE feature flags This change improves the definitions of the assembler's SSE instructions in two ways: - vector instructions that require aligned memory accesses (i.e., most everything pre-AVX) are now noted with an `align` attribute in the AST. This is used for generating the expected `XmmMemAligned` types in `cranelift-codegen-meta` the "right way," resolving the temporary fix introduced in #10417. - previously-added vector instructions did not have the correct feature flags; this change adds the `sse` feature and also tags the applicable instructions with the `compat` feature to allow their use in some future 32-bit target. * asm: disallow duplicate features
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In #10408, the new assembler re-opened an old issue related to unaligned loads with SSE instructions. SSE instructions expect 128-bit aligned loads when using the
m128operand and fault if that is not the case. This had been fixed previously by disallowing load-sinking forXmmMem(#4891) but more recently we had adopted the use ofXmmMemAlignedincranelift-codegen. Since #10316 had no knowledge ofXmmMemAligned(onlyXmmMem), it caused the same kind fault--an OOB trap that was in fact an unaligned load.Why didn't CI catch this? Since all the CI machines have AVX and we do not explicitly test the SSE-only case, these unaligned, sunk loads would use the AVX lowering in CI. AVX loads handle unaligned accesses without a fault. This was only discovered during fuzzing when AVX was disabled (i.e.,
--target x86_64-unknown-linux-gnu).To fix this, this change adopts the
XmmMemAlignedtype in the generated assembler code. This is temporary, though: a more lasting fix should pass along an "alignment required" bit from the assembler AST. In the meantime, this closes #10408.