Cranelift: Fix ABIMachineSpec::gen_add_imm for riscv64#6780
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fitzgen merged 1 commit intobytecodealliance:mainfrom Jul 27, 2023
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Cranelift: Fix ABIMachineSpec::gen_add_imm for riscv64#6780fitzgen merged 1 commit intobytecodealliance:mainfrom
ABIMachineSpec::gen_add_imm for riscv64#6780fitzgen merged 1 commit intobytecodealliance:mainfrom
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It was generating bit-wise and instructions instead of addition instructions. While we are at it, use field literal short hand for a struct literal in riscv64 instruction emission.
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alexcrichton
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* main: (47 commits) Add core dump support to the runtime (bytecodealliance#6513) Resource table tracks child relationships (bytecodealliance#6779) Wasmtime: Move `OnDemandInstanceAllocator` to its own module (bytecodealliance#6790) wasi: Test the stdio streams implementation (bytecodealliance#6764) Don't generate same-named imports in fact modules (bytecodealliance#6783) Wasmtime: Add support for Wasm tail calls (bytecodealliance#6774) Cranelift: Fix `ABIMachineSpec::gen_add_imm` for riscv64 (bytecodealliance#6780) Update the wasm-tools family of crates, disallow empty component types (bytecodealliance#6777) Fix broken link to WASI API documentation (bytecodealliance#6775) A bunch of cleanups for cranelift-codegen-meta (bytecodealliance#6772) Implement component-to-component calls with resources (bytecodealliance#6769) Ignore async_stack_size if async_support is disabled (bytecodealliance#6771) A bunch of minor cleanups (bytecodealliance#6767) Fix flaky tests in preview2 streams (bytecodealliance#6763) Refactor and simplify component trampolines (bytecodealliance#6751) Cranelift: Implement tail calls on riscv64 (bytecodealliance#6749) WASI Preview 2: rewrite streams and pollable implementation (bytecodealliance#6556) cranelift-wasm: Add support for translating Wasm tail calls to CLIF (bytecodealliance#6760) Cranelift: Get tail calls working on aarch64 (bytecodealliance#6723) Implement component model resources in Wasmtime (bytecodealliance#6691) ...
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…iance#6780) It was generating bit-wise and instructions instead of addition instructions. While we are at it, use field literal short hand for a struct literal in riscv64 instruction emission.
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It was generating bit-wise and instructions instead of addition instructions.
While we are at it, use field literal short hand for a struct literal in riscv64 instruction emission.