Increased size of cs_isn.bytes to 33 to be able to hold big EVM instructions#1231
Increased size of cs_isn.bytes to 33 to be able to hold big EVM instructions#1231f0rki wants to merge 1694 commits intocapstone-engine:nextfrom
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33 looks weird though, should we round the size up to some other number? |
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I don't know. It already feels like a lot of wasted memory for all the other archs. |
* normalize tab character in cs
* normalize tab character in cs * normalize in issue mode
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h * Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction * Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h * Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter * Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h * Backport it from: porto703@0db412c * All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly. * Add refactored cs.c for RISCV * Testing all I instructions in test_riscv.c * Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture * Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c * fixed bug related to incorrect initialization of memory after malloc * fix compile bug * Fix compile errors. * move riscv.h to include/capstone * fix indentation issues * fix coding style issues * Fix indentation issues * fix coding style * Move variable declaration to the top of the block * Fix coding indentation * Move some stuff into RISCVMappingInsn.inc * Fix code sytle * remove cs_mode support for RISCV * update asmwriter-inc to LLVM upstream * update the .inc files to riscv upstream * update riscv disassembler function for suport 16bit instructions * update printer & tablegen inc files which have fixed arguments mismatch * update headers and mapping source * add riscv architecture specific test code * fix all RISCV tons of compiler errors * pass final tests * add riscv tablegen patchs * merge with upstream/next * fix cstool missing riscv file * fix root Makefile * add new TableGen patchs for riscv * fix cmakefile.txt of missing one riscv file * fix declaration conflict * fix incompatible declaration type * change riscvc from arch to mode * fix test_riscv warnning * fix code style and add riscv part of test_basic * add RISCV64 mode * add suite for riscv * crack fuzz test * fix getfeaturebits test add riscvc * fix test missing const qualifier warnning * fix testcase type mismatch * fix return value missing * change getfeaturebits test * add test cs files * using a winder type contain the decode string * fix a copy typo * remove useless mode for riscv * change cs file blank type * add repo for update_riscv & fix cstool missing riscv mode * fix typo * add riscv for cstool useage * add TableGen patch for riscv asmwriter * clean ctags file * remove black comment line * fix fuzz related something * fix missing RISCV string of fuzz * update readme, etc.. * add riscv *.s.cs file * add riscv *.s.cs file & clear ctags * clear useless array declarations at capstone_test * update to 5e4069f * update readme change name more formal * change position of riscv after bpf and modify copyright more uniform * clear useless ctags file * change blank with tab in riscv.h * add riscv python bindings * add riscv in __init__.py * fix riscv define value for python binding * fix test_riscv.py typo * add missing riscvc in __init__.py of python bindings * fix alias-insn printer bug, remove useless newline * change inst print delimter from tab to bankspace for travis * add riscv tablegen patch * fix inst output more consistency * add TableGen patch which fix inst output formal * crack the effective address output for detail and change register print function * fix not detail crash bug * change item declaration position at cs_riscv * update riscv.py * change function name more meaningfull * update python binding makefile * fix register enum sequence according to riscvgenreginfo.inc * test function name * add enum s0/fp in riscv.h & update riscv_const.py * add register name enum
* fix bug in displacement offset * fix k0-k7 registers in X86 table.
…e-engine#1702) * mos65xx: use imm field for immediate operand value using the wrong field works on little-endian hosts, but on big-endian the wrong value would be read * mos65xx: set operand mem field to address also in relative modes previously the last operand would have an offset, which doesn't match the printed operand * mos65xx: add bpl instruction to test this demonstrates an address operand with relative addressing
it's a good idea, can you do this continue? |
…ieri/moffset_disp Fix the displacement offset for moffset-encoded operands
fixed library extension to build properly under CYGWIN
Correcting X86 Imm Size
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yes, plz rebase your branch to 'next'. 'master' is not accept to PR
@aquynh any thoughts? |
… EVM instructions (PUSH15 until PUSH32)
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I rebased to next. |
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i hesitate on this PR since it would break the API :-( |
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Alternatively: Would it make sense to move the opcode constant to the |
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Will it make more sense to declare the field Or alternatively declaring The length changing of |
Adding an extra pointer indirection/allocation is less efficient but could help maintain ABI compatibility. It depends on what we want to do. |
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Thank you for the PR! I closed it because it is out of date. With the new auto-sync update for v6 we made many changes to some main architectures and will do also to others. If you still want to merge the changes, please rebase your fix onto the newest |
The EVM arch has a couple of really big instructions, with the biggest one being
PUSH32(with 33 bytes size). Currentlycs_instcan only hold 16 bytes of raw instruction data, which is not enough for EVM. This results in the bytes being truncated to 16 bytes. This didn't really affect the disassembly or theop_str, but if you usecs_inst.sizeorcs_inst.bytesafterwards, it would return wrong data for those big instructions (PUSH15up toPUSH32).