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base-files: improve dnsmasq.time handling for dnssec#2

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ldir-EDB0 wants to merge 2 commits intolede-project:masterfrom
ldir-EDB0:sysfixtimednssec
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base-files: improve dnsmasq.time handling for dnssec#2
ldir-EDB0 wants to merge 2 commits intolede-project:masterfrom
ldir-EDB0:sysfixtimednssec

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@ldir-EDB0
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dnsmasq uses dnsmasq.time to validate if the system clock is current or not. This process is particularly important when dnsmasq's 'dnssec-check-unsigned' option is enabled.

@ConorOG
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ConorOG commented May 12, 2016

Why should fixsystime exclude any file? Can a file be too new?

@ldir-EDB0
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dnsmasq uses the timestamp on dnsmasq.time as a decider on whether to valid dnssec time based signatures. Once system time has gone beyond dnsmasq.time, dnsmasq considers system time valid and starts validating dnssec timestamps. If system time is wrong and you validate timestamps, name resolution in essence stops. This may not be so help if it is ntpd trying to do the lookup :-) The file based solution adopted by dnsmasq used the assumption that systime would be in the 1970s on boot to then be corrected to present by ntpd.

So, if sysfixtime sets the time to newer than dnsmasq.time, time would be considered valid which may have unfortunate consequences.

A different solution would be to have ntpd signal dnsmasq when it has set time for real. That's not the solution I coded for :-)

@jow-
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jow- commented May 13, 2016

@kdarbyshirebryant - the dnsmasq specific file handling should not be added as exception to sysupgrade, you should handle it like that:

The dnsmasq.time exclusion in sysfixtime can stay but we can optimize the find command instead of using a slow shell parsing loop.

I think the following should work: find /etc -type f '!' -path /etc/dnsmasq.time -exec date -r {} +%s \; | sort -nr | head -n1

@ldir-EDB0
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Thank you Jow - I shall take your advice and work on a better version - I'll be back, though it might take a while :-)

@ldir-EDB0
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@jow May I bring your attention to https://patchwork.ozlabs.org/patch/521344/ which discussed (at great length!) a variety to methods for finding the latest file (excluding dnsmasq.time) I'm reminded that the original reason for changing from the original 'find/exec' combination (indeed my original patch used a '!' -path /etc/dnsmasq.time as per your suggestion above) was to reduce CPU usage. Justin explores this a little more in his post in the above mentioned thread.

I'm inclined to use his improved option:
time sh -c 'local file newest; for file in $(find /etc -type f ! -path /etc/dnsmasq.time) ; do [ -z "$newest" -o "$newest" -ot "$file" ] && newest=$file ; done ; [ "$newest" ] && date -r "$newest" +%s'
1463567373
real 0m 0.09s
user 0m 0.09s
sys 0m 0.00s

time find /etc -type f '!' -path /etc/dnsmasq.time -exec date -r {} +%s ; | sort -nr | head -n1
real 0m 1.57s
user 0m 0.06s
sys 0m 0.13s

What do you think?

@jow-
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jow- commented May 18, 2016

I'd say take the faster find command then.

@ldir-EDB0
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Hopefully the latest commits are more what you're looking for :-)

ldir-EDB0 added 2 commits May 18, 2016 19:35
dnsmasq maintains dnsmasq.time across reboots and uses it as a means of
determining if current time is good enough to validate dnssec time
stamps.  By including /etc/dnsmasq.time as a time source for sysfixtime,
the mechanism was effectively defeated because time was set to the
last time that dnsmasq considered current even though that time is in
the past.  Since that time is out of date, dns(sec) resolution would
fail thus defeating any ntp based mechanisms for setting the clock
correctly.

In theory the process is defeated by any files in /etc that are newer
than /etc/dnsmasq.time however dnsmasq now updates the file's timestamp
on process TERM so hopefully /etc/dnsmasq.time is the latest file
timestamp in /etc as part of LEDE shutdown/reboot.

Either way, including /etc/dnsmasq.time as a time source for
sysfixtime is not helpful.
conditionally save dnsmasq.time across sysupgrade
dnsmasq uses /etc/dnsmasq.time as record of the last known good
system time to aid its validation of dnssec timestamps.  dnsmasq
updates the timestamp on process start/stop once it considers the system
time as valid. The timestamp file should be preserved across system
upgrade but should not be included as part of normal configuration
backups to prevent restores corrupting the current timestamp.
@jow-
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jow- commented May 18, 2016

@jow- jow- closed this May 18, 2016
@ldir-EDB0 ldir-EDB0 deleted the sysfixtimednssec branch May 18, 2016 21:38
13hakta added a commit to 13hakta/source that referenced this pull request Feb 9, 2017
Add register and masks for external port lede-project#2
Add RGMII mode setup for external port lede-project#2
Remove unneeded port enabling for RGMII mode as it was already enabled at switch init.

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Feb 9, 2017
Add register and masks for external port lede-project#2
Add RGMII mode setup for external port lede-project#2
Remove unneeded part RGMII as part it was already enabled at setup.

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Feb 9, 2017
Add register and masks for external port lede-project#2
Add RGMII mode setup for external port lede-project#2
Remove unneeded part RGMII as part it was already enabled at setup.

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Feb 9, 2017
Add register and masks for external port lede-project#2
Add RGMII mode setup for external port lede-project#2
Remove unneeded part RGMII as part it was already enabled at setup.

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Feb 10, 2017
Add register and masks for external port lede-project#2
Add RGMII mode setup for external port lede-project#2
Remove unneeded part RGMII as part it was already enabled at setup.

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Feb 10, 2017
Remove unneeded cpu port property, update external interface init
according to mapped ports for RTL8267RB:
ext port #1 = extif0
ext port lede-project#2 = extif1

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Feb 10, 2017
Add register and masks for external port lede-project#2
Add RGMII mode setup for external port lede-project#2
Remove unneeded part RGMII as part it was already enabled at setup.

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Feb 10, 2017
Remove unneeded cpu port property, update external interface init
according to mapped ports for RTL8267RB:
ext port #1 = extif0
ext port lede-project#2 = extif1

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Feb 10, 2017
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports.
RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7).
RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6).
Map ports so that extif0 complies to external port 0 or 1 depending on chip ID.

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Feb 10, 2017
Add register and masks for external port lede-project#2
Add RGMII mode setup for external port lede-project#2
Remove unneeded part RGMII as part it was already enabled at setup.

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Feb 10, 2017
Remove unneeded cpu port property, update external interface init
according to mapped ports for RTL8267RB:
ext port #1 = extif0
ext port lede-project#2 = extif1

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Feb 10, 2017
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports.
RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7).
RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6).
Map ports so that extif0 complies to external port 0 or 1 depending on chip ID.

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Feb 10, 2017
Add register and masks for external port lede-project#2
Add RGMII mode setup for external port lede-project#2
Remove unneeded part RGMII as part it was already enabled at setup.

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Feb 10, 2017
Remove unneeded cpu port property, update external interface init
according to mapped ports for RTL8267RB:
ext port #1 = extif0
ext port lede-project#2 = extif1

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Feb 10, 2017
Add register and masks for external port lede-project#2
Add RGMII mode support for external port lede-project#2
Rewrite method according API, fix bit with bypass line rate.

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Feb 10, 2017
Remove unneeded cpu port property, update external interface init
according to mapped ports for RTL8267RB:
ext port #1 = extif0
ext port lede-project#2 = extif1

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Feb 10, 2017
Remove unneeded cpu port property, update external interface init
according to mapped ports for RTL8267RB:
ext port #1 = extif0
ext port lede-project#2 = extif1

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Jun 18, 2018
Add register and masks for external port lede-project#2
Add RGMII mode support for external port lede-project#2
Rewrite method according API, fix bit with bypass line rate.

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Jun 18, 2018
Remove unneeded cpu port property, update external interface init
according to mapped ports for RTL8267RB:
ext port #1 = extif0
ext port lede-project#2 = extif1

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Jun 18, 2018
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports.
RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7).
RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6).
Map ports so that extif0 complies to external port 0 or 1 depending on chip ID.

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Jun 18, 2018
Add register and masks for external port lede-project#2
Add RGMII mode support for external port lede-project#2
Rewrite method according API, fix bit with bypass line rate.

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Jun 18, 2018
Remove unneeded cpu port property, update external interface init
according to mapped ports for RTL8267RB:
ext port #1 = extif0
ext port lede-project#2 = extif1

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Jun 19, 2018
Update external interface init according to mapped ports for RTL8367RB:
ext port #1 = extif0
ext port lede-project#2 = extif1

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Jun 19, 2018
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports.
RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7).
RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6).
Map ports so that extif0 complies to external port 0 or 1 depending on chip ID.

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Jun 19, 2018
Add register and masks for external port lede-project#2
Add RGMII mode support for external port lede-project#2
Rewrite method according API, fix bit with bypass line rate.

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Jun 19, 2018
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports.
RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7).
RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6).
Map ports so that extif0 complies to external port 0 or 1 depending on chip ID.

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Jun 19, 2018
Add register and masks for external port lede-project#2
Add RGMII mode support for external port lede-project#2
Rewrite method according API, fix bit with bypass line rate.

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Jun 24, 2018
Add RGMII mode support for external port lede-project#2 (RTL8367RB)

Add register and masks for external port lede-project#2.
Rewrite method according to Ralink SDK.
Fix bit with bypass line rate.

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Jun 25, 2018
Update external interface init according to mapped ports for RTL8367RB:
ext port #1 = extif0
ext port lede-project#2 = extif1

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Jun 25, 2018
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports.
RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7).
RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6).
Map ports so that extif0 complies to external port 0 or 1 depending on chip ID.

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta added a commit to 13hakta/source that referenced this pull request Jun 25, 2018
Add RGMII mode support for external port lede-project#2 (RTL8367RB)

Add register and masks for external port lede-project#2.
Rewrite method according to Ralink SDK.
Fix bit with bypass line rate.

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
artynet referenced this pull request in artynet/LEDE Feb 27, 2020
kernel-image: first release of the IPK for updating the system kernel
jow- pushed a commit that referenced this pull request Dec 22, 2020
The Ubiquiti Network airCube AC is a cube shaped device supporting
2.4 GHz and 5 GHz with internal 2x2 MIMO antennas.
It can be powered with either one of:
 - 24v power supply with 3.0mm x 1.0mm barrel plug
 - 24v passive PoE on first LAN port
There are four 10/100/1000 Mbps ports (1 * WAN + 3 * LAN).
First LAN port have optional PoE passthrough to the WAN port.

SoC:       Qualcomm / Atheros AR9342
RAM:       64 MB DDR2
Flash:     16 MB SPI NOR
Ethernet:  4x 10/100/1000 Mbps (1 WAN + 3 LAN)
LEDS:      1x via a SPI controller (not yet supported)
Buttons:   1x Reset
Serial:    1x (only RX and TX); 115200 baud, 8N1

Missing features:
 - LED control is not supported

Physical to internal switch port mapping:
 - physical port #1 (poe in) = switchport 2
 - physical port #2 = switchport 3
 - physical port #3 = switchport 5
 - physical port #4 (wan/poe out) = switchport 4

Factory update is tested and is the same as for Ubiquiti AirCube ISP
hence the shared configuration between that devices.

Signed-off-by: Roman Kuzmitskii <damex.pp@icloud.com>
jow- pushed a commit that referenced this pull request Aug 21, 2021
Rearrange all voltage triplets for "opp_table0" to match the
specifications.  "opp-microvolt" and "opp-microvolt-<name>" triplets
are in order of <target min max>, and NOT <min target max>.

Previously, the CPU would *always* spend its time at the "minimum"
voltage, ignoring the actual intended target.  This is a regression
from previous behavior.

On an NBG6817 with a Qualcomm CPU of PVS bin #2...
(see &opp_table0 -> opp-1725000000 -> opp-microvolt-speed0-pvs2-v0)

* Before:
/usr/bin/tail -n +1 /sys/kernel/debug/opp/cpu0/opp\:1725000000/supply-0/u_volt_*
==> /sys/kernel/debug/opp/cpu0/opp:1725000000/supply-0/u_volt_max <==
1260000

==> /sys/kernel/debug/opp/cpu0/opp:1725000000/supply-0/u_volt_min <==
1200000

==> /sys/kernel/debug/opp/cpu0/opp:1725000000/supply-0/u_volt_target <==
1140000

* After:
/usr/bin/tail -n +1 /sys/kernel/debug/opp/cpu0/opp\:1725000000/supply-0/u_volt_*
==> /sys/kernel/debug/opp/cpu0/opp:1725000000/supply-0/u_volt_max <==
1260000

==> /sys/kernel/debug/opp/cpu0/opp:1725000000/supply-0/u_volt_min <==
1140000

==> /sys/kernel/debug/opp/cpu0/opp:1725000000/supply-0/u_volt_target <==
1200000

To check voltages and frequencies at run time, use...
/bin/cat /sys/kernel/debug/regulator/regulator_summary &&
  /bin/cat /sys/kernel/debug/clk/clk_summary | grep "hfpll"

See
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/Documentation/devicetree/bindings/opp/opp.txt?h=v5.4.142#n91

Fixes: 1e25423 ("ipq806x: refresh dtsi patches")

Signed-off-by: Shane Synan <digitalcircuit36939@gmail.com>
Reviewed-by: Ansuel Smith <ansuelsmth@gmail.com>
[commit message style cleanup, another kernel refresh]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
jow- pushed a commit that referenced this pull request Nov 27, 2021
Follow up to commit 565b62c. Managed to
hit the very same issue again while playing with the NOR SPL builds.

Signed-off-by: Mathias Kresin <dev@kresin.me>
jow- pushed a commit that referenced this pull request Nov 27, 2021
Follow up to commit 8fb714e. Managed to
hit the very same issue again while playing with the NOR SPL builds.

Signed-off-by: Mathias Kresin <dev@kresin.me>
jow- pushed a commit that referenced this pull request Nov 27, 2021
Follow up to commit c744798. Managed to
hit the very same issue again while playing with the NOR SPL builds.

Signed-off-by: Mathias Kresin <dev@kresin.me>
jow- pushed a commit that referenced this pull request Jan 21, 2022
This board has 512MiB of RAM like the R7800, and the VDSL modem is
attached to the second PCIe port.

Signed-off-by: David Woodhouse <dwmw2@infradead.org>
openwrt-bot pushed a commit that referenced this pull request Feb 24, 2023
Increased size of the 5.15 kernel requires bumping BZ_TEXT_START again.
Without this CFE hangs at the:
Starting program at 0x80001000

This fixes booting 5.15 based mips74k images on:
1. BCM4706 (Luxul XWR-1750)
2. BCM5357B0 (Linksys E1000 V2.1)
3. BCM47186B0 (Luxul XWR-600)
4. BCM5358 (Linksys E2500 V3)

It isn't needed but also doesn't break:
1. BCM5354 (Asus WL-500gP V2)

Ref: 4cd97e4 ("bcm47xx: relocate LZMA loader")
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
lynxis pushed a commit to lynxis/source that referenced this pull request Apr 13, 2023
mediatek/mt7622: set label_mac and wan mac
openwrt-bot pushed a commit that referenced this pull request May 20, 2023
Iomega Storcenter ix4-200d is a four-bay SATA NAS powered by a Marvell
Kirkwood SoC clocked at 1.2GHz. It has 512MB of RAM and 32MB of
flash memory, 3x USB 2.0 and 2x 1Gbit/s NIC

Specification:
- SoC: Marvell Kirkwood 88F6281
- CPU/Speed: 1200Mhz
- Flash size: 32 MiB
- RAM: 512MB
- LAN: 2x 1Gbit/s
- 3x USB 2.0

Notes:
- The blue drive LED is triggered by HDD activity, it can not be controlled
  via GPIO.
- The LCD screen requires proprietary code and does not function at this time.
- Due to a kernel-related issue with the Marvell 88SE6121 SATA controller,
  currently only trays numbered #3 and #4 work, #1 and #2 do not. [1]

Serial pinout:

    CN4
    --------------
    | 10 8 6 4 2 |
    |  9 7 5 3 1 |
    -------------- PIN 1 Mark (fat line)

     1 = RXD
     4 = TXD
     6 = GND
     9 = 3.3V (not necessary to connect)

Installation instructions:
1. download initramfs-uImage and copy into tftp server
2. connect the tftp server to network port #1
3. access uboot environment with serial cable and run

    setenv mainlineLinux yes
    setenv arcNumber 1682
    setenv console 'console=ttyS0,115200n8'
    setenv mtdparts 'mtdparts=orion_nand:0x100000@0x000000(u-boot)ro,0x20000@0xA0000(u-boot environment)ro,0x300000@0x100000(kernel),0x1C00000@0x400000(ubi)'
    setenv bootargs_root 'root='
    setenv bootcmd 'setenv bootargs ${console} ${mtdparts} ${bootargs_root}; nand read.e 0x800000 0x100000 0x300000; bootm 0x00800000'
    saveenv
    setenv serverip 192.168.1.1
    setenv ipaddr 192.168.1.2
    tftpboot 0x00800000 [initramfs-uImage filename]
    bootm 0x00800000

4. connect to LAN on network port #2, log into openwrt and sysupgrade to install into flash

[1] https://bugzilla.kernel.org/show_bug.cgi?id=216094

Signed-off-by: Sander van Deijck <sander@vandeijck.com>
(aligned FROM from signed-off. LED+key rename, whitespace removal)
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
openwrt-bot pushed a commit that referenced this pull request Jan 8, 2024
Hardware specification:
  SoC: MediaTek MT7981B 2x A53
  Flash: 16MB NOR
  RAM: 256MB
  Ethernet: 2x 10/100/1000 Mbps
  Switch: MediaTek MT7531AE
  WiFi: MediaTek MT7976C
  Button: Reset
  Power: DC 12V 1A, PoE 802.3af 48V

Flash instructions:

Option #1 - SSH

  I was able to SSH into the stock firmware of my device.

  1. Attach the router to the network
  2. Use scp (-O) to copy the sysupgrade image
  3. Connect using SSH and run `sysupgrade -n`

Option #2 - U-Boot

  One way to use the bootloader for flashing is using TFTP:

  1. Connect to the router using an ethernet cable
  2  Spin up a TFTP server serving the sysupgrade file
  3. Open the case and attach a UART
  4. Attach power to the router and interrupt the countdown by pressing
     any key
  5. Select option #2 (Upgrade firmware)
  6. Enter IP address information and image name
  7. Wait patiently

Co-Authored-By: Enrique Rodríguez Valencia <enrique.rodriguez@galgus.net>
Co-Authored-By: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Leon M. Busch-George <leon@georgemail.eu>
openwrt-bot pushed a commit that referenced this pull request Feb 29, 2024
Disabled services should be kept disabled after sysupgrade. This can be
easily handled using a proper uci-defaults script.

Extend sysupgrade to check for disabled services, generate uci-defaults
script disabling them and include it in backup.

Cc: Christian Marangi <ansuelsmth@gmail.com>
Cc: Jo-Philipp Wich <jo@mein.io>
Cc: Jonas Gorski <jonas.gorski@gmail.com>
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Acked-by: Jo-Philipp Wich <jo@mein.io>
openwrt-bot pushed a commit that referenced this pull request Jul 4, 2024
Hardware specification:
  SoC: MediaTek MT7981B 2x A53
  Flash: 16MB NOR
  RAM: 256MB
  Ethernet: 2x 10/100/1000 Mbps
  Switch: MediaTek MT7531AE
  WiFi: MediaTek MT7976C
  Button: Reset
  Power: DC 12V 1A, PoE 802.3af 48V

Flash instructions:

Option #1 - SSH

  I was able to SSH into the stock firmware of my device.

  1. Attach the router to the network
  2. Use scp (-O) to copy the sysupgrade image
  3. Connect using SSH and run `sysupgrade -n`

Option #2 - U-Boot

  One way to use the bootloader for flashing is using TFTP:

  1. Connect to the router using an ethernet cable
  2  Spin up a TFTP server serving the sysupgrade file
  3. Open the case and attach a UART
  4. Attach power to the router and interrupt the countdown by pressing
     any key
  5. Select option #2 (Upgrade firmware)
  6. Enter IP address information and image name
  7. Wait patiently

Co-Authored-By: Enrique Rodríguez Valencia <enrique.rodriguez@galgus.net>
Co-Authored-By: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Leon M. Busch-George <leon@georgemail.eu>
(cherry picked from commit b4086f4)
openwrt-bot pushed a commit that referenced this pull request May 31, 2025
Every time "sysupgrade -b -" runs it would generate a new
(synthetic) "/etc/uci-defaults/10_disable_services" file with
the current time as the modified time.  This unfortunately
creates a non-deterministic tarball, so if you run a cron job
to save your state, you don't have a trivial way of seeing if
it changed or not without unpacking the archive, deleting this
file, and comparing the entire directory tree to the previous
backup.

Fixes: #16145
Fixes: 0ad062a ("base-files: sysupgrade: include uci-defaults script disabling services #2")
Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
openwrt-bot pushed a commit that referenced this pull request Jun 22, 2025
Suppress output from `/etc/init.d/service enabled` to avoid corrupting
of the sysupgrade tarball.

Fixes: 0ad062a ("base-files: sysupgrade: add uci-defaults script disabling services #2")
Signed-off-by: Niall McGee <niall.mcgee@bt.com>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
openwrt-bot pushed a commit that referenced this pull request Jul 19, 2025
The ix4-200d is a 4 bay NAS supported since OpenWrt 23.05. Drive trays
controller. Due to a kernel-related issue with the SATA controller,
trays #1 and #2 were not recognized. This issue has been fixed in
kernel 6.10, so with the adoption of kernel 6.12 in the Kirkwood
target trays #1 and #2 can now be made accessible. This requires the
kmod-ata-ahci package, which this commit adds as default to the
makefile.

Signed-off-by: Sander van Deijck <sander@vandeijck.com>
Link: openwrt/openwrt#19435
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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3 participants