e2fsprogs: update to 1.42.13#5
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Update e2fsprogs to v1.42.13 from 1.42.12 Signed-off-by: Kevin Darbyshire-Bryant <kevin@darbyshire-bryant.me.uk>
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Pulled into my staging tree: https://git.lede-project.org/?p=lede/jow/staging.git;a=commit;h=ef70cd79ae80f0d1ce6ef4cd07653a2e6bbb3b37 |
13hakta
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Feb 10, 2017
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports. RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7). RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6). Map ports so that extif0 complies to external port 0 or 1 depending on chip ID. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta
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Feb 10, 2017
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports. RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7). RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6). Map ports so that extif0 complies to external port 0 or 1 depending on chip ID. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta
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Feb 16, 2017
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports. RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7). RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6). Map ports so that extif0 complies to external port 0 or 1 depending on chip ID. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta
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Feb 19, 2017
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports. RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7). RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6). Map ports so that extif0 complies to external port 0 or 1 depending on chip ID. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta
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Feb 19, 2017
On RTL8367R-VB/RB chips present 2 external ports of maximum 3. Port lede-project#7 works in RGMII mode only and present only on RTL8367RB. Ports are numbered sequentially and so port lede-project#5 must be avoided as only ports 0-4,6,7 are present on board. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta
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Mar 22, 2017
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports. RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7). RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6). Map ports so that extif0 complies to external port 0 or 1 depending on chip ID. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta
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Mar 22, 2017
On RTL8367R-VB/RB chips present 2 external ports of maximum 3. Port lede-project#7 works in RGMII mode only and present only on RTL8367RB. Ports are numbered sequentially and so port lede-project#5 must be avoided as only ports 0-4,6,7 are present on board. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta
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Apr 16, 2017
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports. RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7). RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6). Map ports so that extif0 complies to external port 0 or 1 depending on chip ID. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta
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Apr 16, 2017
On RTL8367R-VB/RB chips present 2 external ports of maximum 3. Port lede-project#7 works in RGMII mode only and present only on RTL8367RB. Ports are numbered sequentially and so port lede-project#5 must be avoided as only ports 0-4,6,7 are present on board. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
admiral0
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Apr 25, 2017
13hakta
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May 16, 2017
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports. RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7). RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6). Map ports so that extif0 complies to external port 0 or 1 depending on chip ID. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta
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May 16, 2017
On RTL8367R-VB/RB chips present 2 external ports of maximum 3. Port lede-project#7 works in RGMII mode only and present only on RTL8367RB. Ports are numbered sequentially and so port lede-project#5 must be avoided as only ports 0-4,6,7 are present on board. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
kovz
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Jul 20, 2017
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports. RTL8367RB has ports indexed as lede-project#1,lede-project#2 (PHY lede-project#6, lede-project#7). RTL8367R-VB has ports indexed as #0,lede-project#1 (PHY lede-project#5,lede-project#6). Map ports so that extif0 complies to external port 0 or 1 depending on chip ID. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
kovz
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Jul 20, 2017
On RTL8367R-VB/RB chips present 2 external ports of maximum 3. Port lede-project#7 works in RGMII mode only and present only on RTL8367RB. Ports are numbered sequentially and so port lede-project#5 must be avoided as only ports 0-4,6,7 are present on board. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
kovz
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Sep 1, 2017
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports. RTL8367RB has ports indexed as lede-project#1,lede-project#2 (PHY lede-project#6, lede-project#7). RTL8367R-VB has ports indexed as #0,lede-project#1 (PHY lede-project#5,lede-project#6). Map ports so that extif0 complies to external port 0 or 1 depending on chip ID. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
kovz
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Sep 1, 2017
On RTL8367R-VB/RB chips present 2 external ports of maximum 3. Port lede-project#7 works in RGMII mode only and present only on RTL8367RB. Ports are numbered sequentially and so port lede-project#5 must be avoided as only ports 0-4,6,7 are present on board. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta
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Jun 17, 2018
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports. RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7). RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6). Map ports so that extif0 complies to external port 0 or 1 depending on chip ID. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta
added a commit
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Jun 17, 2018
On RTL8367R-VB/RB chips present 2 external ports of maximum 3. Port lede-project#7 works in RGMII mode only and present only on RTL8367RB. Ports are numbered sequentially and so port lede-project#5 must be avoided as only ports 0-4,6,7 are present on board. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta
added a commit
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Jun 17, 2018
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports. RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7). RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6). Map ports so that extif0 complies to external port 0 or 1 depending on chip ID. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta
added a commit
to 13hakta/source
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Jun 17, 2018
On RTL8367R-VB/RB chips present 2 external ports of maximum 3. Port lede-project#7 works in RGMII mode only and present only on RTL8367RB. Ports are numbered sequentially and so port lede-project#5 must be avoided as only ports 0-4,6,7 are present on board. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta
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Jun 17, 2018
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports. RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7). RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6). Map ports so that extif0 complies to external port 0 or 1 depending on chip ID. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta
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Jun 17, 2018
On RTL8367R-VB/RB chips present 2 external ports of maximum 3. Port lede-project#7 works in RGMII mode only and present only on RTL8367RB. Ports are numbered sequentially and so port lede-project#5 must be avoided as only ports 0-4,6,7 are present on board. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta
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Jun 18, 2018
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports. RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7). RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6). Map ports so that extif0 complies to external port 0 or 1 depending on chip ID. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta
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Jun 18, 2018
On RTL8367R-VB/RB chips present 2 external ports of maximum 3. Port lede-project#7 works in RGMII mode only and present only on RTL8367RB. Ports are numbered sequentially and so port lede-project#5 must be avoided as only ports 0-4,6,7 are present on board. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta
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Jun 18, 2018
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports. RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7). RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6). Map ports so that extif0 complies to external port 0 or 1 depending on chip ID. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta
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Jun 18, 2018
On RTL8367R-VB/RB chips present 2 external ports of maximum 3. Port lede-project#7 works in RGMII mode only and present only on RTL8367RB. Ports are numbered sequentially and so port lede-project#5 must be avoided as only ports 0-4,6,7 are present on board. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta
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Jun 19, 2018
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports. RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7). RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6). Map ports so that extif0 complies to external port 0 or 1 depending on chip ID. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta
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Jun 19, 2018
On RTL8367R-VB/RB chips present 2 external ports of maximum 3. Port lede-project#7 works in RGMII mode only and present only on RTL8367RB. Ports are numbered sequentially and so port lede-project#5 must be avoided as only ports 0-4,6,7 are present on board. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta
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to 13hakta/source
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Jun 19, 2018
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports. RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7). RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6). Map ports so that extif0 complies to external port 0 or 1 depending on chip ID. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta
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Jun 19, 2018
On RTL8367R-VB/RB chips present 2 external ports of maximum 3. Port lede-project#7 works in RGMII mode only and present only on RTL8367RB. Ports are numbered sequentially and so port lede-project#5 must be avoided as only ports 0-4,6,7 are present on board. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta
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Jun 24, 2018
Ports are handled sequentially and indexed from 0 to 7. But boards has different numeration and port functionality so absent port must be avoided. On RTL8367R-VB/RB chips present 2 external ports of maximum 3. RTL8367RB has ports numbered 0-4,6,7. Must skip lede-project#5. RTL8367R-VB has ports numbered 0-6. Must skip lede-project#7. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta
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Jun 25, 2018
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports. RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7). RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6). Map ports so that extif0 complies to external port 0 or 1 depending on chip ID. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
13hakta
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Jun 25, 2018
Ports are handled sequentially and indexed from 0 to 7. But boards has different numeration and port functionality so absent port must be avoided. On RTL8367R-VB/RB chips present 2 external ports of maximum 3. RTL8367RB has ports numbered 0-4,6,7. Must skip lede-project#5. RTL8367R-VB has ports numbered 0-6. Must skip lede-project#7. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
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Jan 20, 2025
Ruckus R500 datasheet: https://webresources.ruckuswireless.com/datasheets/r500/ds-ruckus-r500.html Specifications: SoC: 720Mhz QCA9558 RAM: 256MB Storage: 64MB of FLASH (SPI NOR - S25FL512S) 1x AR8327 GB switch Ethernet: 1x1000M port #3 on AR8327, 1x1000M (802.3at POE), port #5 on AR8327 Wireless: QCA988X HW2.0 802.11ac AR9550 2.4GHz 802.11b/g/n 5x GPIO LED 1x GPIO Reset Button 1x DC Jack 12v 1x UART, 3.3v, 115200 1x TPM, SLB9645TT12 2x Beamforming antennas configured via 74LV164 MAC addresses: 1. art 0x807E | Factory bridged | f0:3e:90:XX:XX:80 | 2. art 0x66 | eth0 | f0:3e:90:XX:XX:83 | (port 5, cpu port 6) - PoE port 3. art 0x6c | eth1 | f0:3e:90:XX:XX:84 | (port 3, cpu port 0) - non PoE port Serial console: 115200-8-N-1 on internal H4 header. Pinout: H1 ----------- |1|x|3|4|5| ----------- Pin 1 is near the "H4" marking. 1 - RX x - no pin 3 - VCC (3.3V) 4 - GND 5 - TX JTAG: Connector H2, similar to MIPS eJTAG, standard, unpoulated. H9 ---------------------- |2 |4 |6 |8 |10|12|14| ---------------------- |1 |3 |5 |7 |9 |11|13| ---------------------- 3 - TDI 5 - TDO 7 - TMS 9 - TCK 2,4,6,8,10 - GND 14 - Vref 1,11,12,13 - Not connected I²C: connector H2, near power LED, unpopulated: ------ |1|2|3 ------ H2 1 - SCL 2 - SDA 3 - GND Installation: Serial Port/TFTP 1. Setup tftp server on the local network 2. Connect to UART with TTL 3. Interupt U-boot process with Ctrl-C 4. Setup appropriate ipaddr and serverip in setenv: - setenv ipaddr 192.168.1.1 - setenv serverip 192.168.1.2 5. On TFTP Server - copy openwrt-ath79-generic-ruckus_r500-initramfs-kernel.bin to /srv/tftp 6. On R500 boot into initrd image - tftpboot 0x81000000 openwrt-ath79-generic-ruckus_r500-initramfs-kernel.bin - bootm 0x81000000 7. On TFTP server - scp -O openwrt-ath79-generic-ruckus_r500-squashfs-sysupgrade.bin root@192.168.1.1:/tmp 8. Ensure the boot command is set before flashing the image: fw_setenv bootcmd 'bootm 0xbf1c0000' 9. On R500 - sysupgrade /tmp/openwrt-ath79-generic-ruckus_r500-squashfs-sysupgrade.bin 10. If not done in 8; set boot command from U-boot shell itself: - setenv bootcmd bootm 0xbf1c0000 - saveenv - reset This patch adapted from https://github.com/victhor393/openwrt-ruckus-r500/tree/ruckus-r500-master Signed-off-by: Damien Mascord <tusker@tusker.org> - Heavily refactored the device tree - Extended commit message - Documented onboad connectors - Refactored MAC and calibration data setups to use nvmem-layout - Made both network interfaces LAN ports and bridge them, this makes more sense for an access point and is consistent with the rest of Ruckus APs. - Enable lzma-loader for compressed initramfs - Enabled the optional internal USB port - Added missing LEDs and according pinctrl settings - Added reserved memory region used for bootloader communication - Added the bit-banged I²C bus and onboard TPM - Refactored boot scheme and flash layout to match earlier Ruckus devices and maximize usable space for user data. Quirks: - H7 is the physical presence switch for the SLB9645TT12 TPM. TODO: - Link state reporting on the Ethernet ports doesn't work and both ports report "up" due to limitation of swconfig ar8327 driver. With DSA conversion, this shall be rectified. - Locate 2nd shift register (U7) controlling beamforming antennas, probably on ath10k GPIOs which are currently unsupported in the driver. For this, there is a device tree node describing that - but explicitly disabled. - At the moment of adding support, there is an endianness bug in the TPM driver causing it to not detect the TPM module because of ID mismatch. Signed-off-by: Lech Perczak <lech.perczak@gmail.com> Link: openwrt/openwrt#17550 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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Update e2fsprogs to v1.42.13 from 1.42.12
Signed-off-by: Kevin Darbyshire-Bryant kevin@darbyshire-bryant.me.uk