Backport bclk clock control to GLK branch #4249

brentlu · 2021-05-26T10:05:58Z

This PR is for ODM/codec vendor validation and review

The series of patches are originated from #4219 which is working on master branch. Since GLK branch is ancient, the implementation of bclk clock control is much simpler here but the idea is the same.

lgirdwood · 2021-05-26T10:44:27Z

@slawblauciak @mwasko fyi.

plbossart · 2021-05-26T14:57:12Z

let's wait that the code is agreed on with the main branch, this should be a backport and aligned with main.

I would also like the topology changes to be applied on the main branch so that we can test all this with CI. @bardliao can you take the topology patches and apply them to your PR #4219 ?

brentlu · 2021-05-26T15:19:09Z

@plbossart yes, we will wait main branch finalized and see what's need to be ported to here. I've validated this PR on customer device and this is the result from oscilliscope:

both bclk and fsync start toggling in hw_param with correct frequency
both bclk and fsync disabled in hw_free.

As a side effect, this PR also fixes da7219 which PLL locks on fsync...

plbossart · 2021-05-26T15:50:49Z

As a side effect, this PR also fixes da7219 which PLL locks on fsync...

That's why I'd like this change to become the default for all I2S codecs ;-)

bardliao · 2021-05-27T05:10:53Z

let's wait that the code is agreed on with the main branch, this should be a backport and aligned with main.

I would also like the topology changes to be applied on the main branch so that we can test all this with CI. @bardliao can you take the topology patches and apply them to your PR #4219 ?

Yes, I took the topology patches with slight modification to PR #4219

brentlu · 2021-06-07T02:09:45Z

update to sync with #4288

brentlu · 2021-06-07T04:16:47Z

measure the signal of this backport:

bclk starts long before fsync in prepare(), then fsync starts with data with one zero sample ahead

fsync stops toggling first, then bclk stops 5.84us later

plbossart · 2021-06-07T13:02:19Z

Thanks @brentlu just to be clear.
Are you saying the results are now OK and all problems with CS42L42 are solved with this PR?

lyakh · 2021-06-08T06:13:01Z

src/drivers/intel/cavs/ssp.c

+
+	spin_lock(&dai->lock);
+
+	trace_ssp("ssp_hw_free()");


this doesn't have to be under the lock

i think we need the lock to protect the ssp->state

@brentlu I meant the trace_ssp("ssp_hw_free()"); line

it's done. thanks for review

brentlu · 2021-06-09T07:13:07Z

@plbossart both ODM and codec vendor could not find problem in this backport. Codec vendor still need to check the performance since bclk frequency is changed but basic function is ok.

plbossart · 2021-06-09T14:21:56Z

@plbossart both ODM and codec vendor could not find problem in this backport. Codec vendor still need to check the performance since bclk frequency is changed but basic function is ok.

Good to know, thanks @brentlu
I'll try to finish up the main branch this week, too many things to do at the moment.

The DAI_CONFIG IPC is currently used both for hw_params and hw_free. For some DAIs, there are hacky ways with e.g. invalid DMA channels to indicate a hw_free. Rather than adding a new IPC for hw_params and hw_free, let's add a flag that indicates if the DAI_CONFIG is really applied during a hw_params or hw_free stage. This is tagged as a ABI 3.19 change. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> (cherry picked from commit 0792297) Signed-off-by: Brent Lu <brent.lu@intel.com>

Add two clks_control bits. MCLK and/or BCLK will start during hw_params and stop during hw_free if the corresponding bit is set. This is tagged as a ABI 3.19 change. Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> (cherry picked from commit f46c144) Signed-off-by: Brent Lu <brent.lu@intel.com>

This will help identify support for SSP BCLK/MCLK changes. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> (cherry picked from commit 2c06163) Signed-off-by: Brent Lu <brent.lu@intel.com>

Some codecs need the SSP bit clock to start before data is provided, and conversely the bit clock to remain active until the hw_free stage. For backwards-compatibility with older kernels, the SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_ES and SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_ES bitfields are used to set an internal state in the ssp->clk_active field. This helps deals with the case where a topology sets these bits but the older kernel does not make use of the modified IPC. While we are at it, add clearer info traces for SSP configurations. Note that the FSYNC only starts when DMA transfers are enabled in the .trigger stage. This is by-design, the FSYNC will only start if the FIFO is not empty. During the prepare stages the DMA transfers are not enabled so the FIFOs are empty. To enable the FSYNC at an earlier stage, we would need a major surgery in the SOF architecture, or we would need to start zero-based DMA transfers. Co-developed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> (cherry picked from commit a0c1758) Signed-off-by: Brent Lu <brent.lu@intel.com>

The current code does not follow recommended programming sequences: TSRE and RSRE should be set before SSE and conversely cleared before SSE. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> (cherry picked from commit 99193ab) Signed-off-by: Brent Lu <brent.lu@intel.com>

Define the SSP_CC_MCLK/BCLK_ES bit to be used in SSP_CONFIG_DATA macro to enable mclk/bclk on hw_params and disable malk/bclk on hw_free. Signed-off-by: Brent Lu <brent.lu@intel.com> Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> (cherry picked from commit 61e4cd7) Signed-off-by: Brent Lu <brent.lu@intel.com>

Add support for cs42l42 running on GLK boards. There is a 10 ms BCLK delay in the master branch version to avoid the noise on TX path. However, this feature is not supported on GLK production branch yet so we remove it for now. Signed-off-by: Brent Lu <brent.lu@intel.com> (cherry picked from commit 45ce11022b40fe0fe8d998ee3f93a74b53fb7fd0) Signed-off-by: Brent Lu <brent.lu@intel.com>

Enable the bclk clock control for SSP2. Note that this impacts existing GLK-based chromebooks as well as newer hardware. Signed-off-by: Brent Lu <brent.lu@intel.com> Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> (cherry picked from commit 7199c68) Signed-off-by: Brent Lu <brent.lu@intel.com>

By changing bclk to 2.4MHz, we can use XTAL as clock source and reduce power consumption. Signed-off-by: Brent Lu <brent.lu@intel.com> (cherry picked from commit 5abd8a9) Signed-off-by: Brent Lu <brent.lu@intel.com>

Changing SSP2 configuration to use 24-bit sample bitwidth. Signed-off-by: Brent Lu <brent.lu@intel.com> (cherry picked from commit 44cc184dee0da1bcb9e1edd54d301b838b54c856) Signed-off-by: Brent Lu <brent.lu@intel.com>

brentlu · 2021-06-24T16:10:20Z

based on the #4288 with topology changes to use 2.4MHz bclk and 24-bit sample width

lgirdwood · 2021-06-30T10:56:24Z

@mwasko @slawblauciak this one is for you.

mwasko · 2021-06-30T11:59:33Z

@brentlu I would recommend to create a separate branch for this change to avoid mess on release code that took place quite a long time ago. If you want to apply this fix on top of glk-012-stable-branch then I would like to propose to create glk-012-hot-fix-1 branch for that.

brentlu · 2021-07-05T13:37:34Z

Hi @mwasko,
Sure, no problem. I found that I could create a branch myself. Thanks for advise.

brentlu requested review from a team, lbetlej, lgirdwood, mmaka1, plbossart and ranj063 as code owners May 26, 2021 10:05

brentlu marked this pull request as draft May 26, 2021 10:09

brentlu requested a review from bardliao May 26, 2021 10:11

plbossart mentioned this pull request May 26, 2021

topology: sof-glk-da7219: add support for cs42l42 #4134

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brentlu force-pushed the glk-ssp-clock branch 2 times, most recently from 557dabc to 4328afc Compare June 6, 2021 16:31

brentlu mentioned this pull request Jun 7, 2021

SSP BLCK and MCLK early start - take3 #4288

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lyakh reviewed Jun 8, 2021

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brentlu force-pushed the glk-ssp-clock branch from e5ed1e5 to 3424102 Compare June 15, 2021 05:14

plbossart and others added 3 commits June 21, 2021 09:41

ABI: bump level to 3.8

2dbb0f8

This will help identify support for SSP BCLK/MCLK changes. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> (cherry picked from commit 2c06163) Signed-off-by: Brent Lu <brent.lu@intel.com>

brentlu force-pushed the glk-ssp-clock branch from 3424102 to ce1f8b9 Compare June 21, 2021 05:28

bardliao and others added 2 commits June 24, 2021 22:01

brentlu added 5 commits June 24, 2021 22:02

topology: sof-glk-cs42l42: using 2.4MHz bclk

557bfee

By changing bclk to 2.4MHz, we can use XTAL as clock source and reduce power consumption. Signed-off-by: Brent Lu <brent.lu@intel.com> (cherry picked from commit 5abd8a9) Signed-off-by: Brent Lu <brent.lu@intel.com>

topology: sof-glk-cs42l42: using 24-bit sample on SSP2

42e25fa

Changing SSP2 configuration to use 24-bit sample bitwidth. Signed-off-by: Brent Lu <brent.lu@intel.com> (cherry picked from commit 44cc184dee0da1bcb9e1edd54d301b838b54c856) Signed-off-by: Brent Lu <brent.lu@intel.com>

brentlu force-pushed the glk-ssp-clock branch from ce1f8b9 to 42e25fa Compare June 24, 2021 15:59

brentlu added GLK Applies to Gemini Lake platform chrome Chromebooks or ChromeOS labels Jun 24, 2021

brentlu changed the title ~~bclk clock control for GLK branch~~ Backport bclk clock control to GLK branch Jun 24, 2021

brentlu marked this pull request as ready for review June 24, 2021 16:14

brentlu changed the base branch from glk-012-stable-branch to glk-012-hot-fix-1 July 7, 2021 02:05

brentlu merged commit 2a13eac into thesofproject:glk-012-hot-fix-1 Jul 13, 2021

Backport bclk clock control to GLK branch #4249

Backport bclk clock control to GLK branch #4249

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