Skip to content

arch/riscv: Unify 32/64 implementations and remove dead ports #2822

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom
Closed
btashton wants to merge 1 commit into from
Closed

arch/riscv: Unify 32/64 implementations and remove dead ports #2822

btashton wants to merge 1 commit into from

Conversation

@btashton
Copy link
Contributor

@btashton btashton commented Feb 8, 2021

Summary

Unify the 32 and 64 bit RISC-V arch and as part of this also drop:

  • nr5m100 -- Non-public custom implementation
  • gap8 -- Custom non-standard RISC-V architecture.

Impact

Testing

Not ready for merge!

btashton
btashton commented Feb 8, 2021
View reviewed changes
This was linked to issues Feb 8, 2021
Merge rv32im and rv64gc into one #2593
Closed
Should we remove the support of too old and incompatible risc-v chip(gap8 and nr5m100)? #2594
Closed
xiaoxiang781216
xiaoxiang781216 reviewed Feb 8, 2021
View reviewed changes
This was referenced Feb 15, 2021
Merged
Closed
@Ouss4 Ouss4 mentioned this pull request Mar 11, 2021
Merged
@xiaoxiang781216 xiaoxiang781216 mentioned this pull request Dec 26, 2021
Merged
@xiaoxiang781216
Copy link
Contributor

xiaoxiang781216 commented Jan 1, 2022

Will be done step by step:
#5076
#5092
#5097
#5103
#5106
#5115
#5123
#5135

@xiaoxiang781216 xiaoxiang781216 removed a link to an issue Jan 11, 2022
Merge rv32im and rv64gc into one #2593
Closed
@xiaoxiang781216
Copy link
Contributor

xiaoxiang781216 commented Jan 11, 2022

Let's track the merge in #2822 instead.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Reviewers

@xiaoxiang781216 xiaoxiang781216 xiaoxiang781216 left review comments

@jerpelea jerpelea Awaiting requested review from jerpelea jerpelea will be requested when the pull request is marked ready for review jerpelea is a code owner

@raiden00pl raiden00pl Awaiting requested review from raiden00pl raiden00pl will be requested when the pull request is marked ready for review raiden00pl is a code owner

@acassis acassis Awaiting requested review from acassis acassis will be requested when the pull request is marked ready for review acassis is a code owner

@gustavonihei gustavonihei Awaiting requested review from gustavonihei gustavonihei will be requested when the pull request is marked ready for review gustavonihei is a code owner

@masayuki2009 masayuki2009 Awaiting requested review from masayuki2009 masayuki2009 will be requested when the pull request is marked ready for review masayuki2009 is a code owner

@pussuw pussuw Awaiting requested review from pussuw pussuw will be requested when the pull request is marked ready for review pussuw is a code owner

@lupyuen lupyuen Awaiting requested review from lupyuen lupyuen will be requested when the pull request is marked ready for review lupyuen is a code owner

@anchao anchao Awaiting requested review from anchao anchao will be requested when the pull request is marked ready for review anchao is a code owner

@fdcavalcanti fdcavalcanti Awaiting requested review from fdcavalcanti fdcavalcanti will be requested when the pull request is marked ready for review fdcavalcanti is a code owner

@hartmannathan hartmannathan Awaiting requested review from hartmannathan hartmannathan will be requested when the pull request is marked ready for review hartmannathan is a code owner

@Ouss4 Ouss4 Awaiting requested review from Ouss4 Ouss4 will be requested when the pull request is marked ready for review Ouss4 is a code owner

@Donny9 Donny9 Awaiting requested review from Donny9 Donny9 will be requested when the pull request is marked ready for review Donny9 is a code owner

@adamfeuer adamfeuer Awaiting requested review from adamfeuer adamfeuer will be requested when the pull request is marked ready for review adamfeuer is a code owner

Assignees

No one assigned

Labels

None yet

Projects

None yet

Milestone

No milestone

Development

Successfully merging this pull request may close these issues.

Should we remove the support of too old and incompatible risc-v chip(gap8 and nr5m100)?

2 participants

@btashton @xiaoxiang781216